METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A LOW K DIELECTRIC
First Claim
1. A semiconductor fabrication process, comprising:
- forming an interlevel dielectric (ILD) overlying a substrate of a semiconductor wafer wherein forming the ILD comprises;
forming a low K dielectric overlying a semiconductor substrate of the wafer, wherein a dielectric constant of the low K dielectric is less than or equal to 3.0;
forming an organic, silicon-oxide, glue layer dielectric overlying the low K dielectric; and
forming a CMP stop layer dielectric overlying the glue layer dielectric;
forming a void in the ILD;
depositing a conductive material over the wafer to fill the void; and
removing portions of the conductive material exterior to the void by polishing the wafer with a CMP process and terminating the CMP process on the CMP stop layer dielectric.
19 Assignments
0 Petitions
Accused Products
Abstract
A backend semiconductor fabrication process includes forming an interlevel dielectric (ILD) overlying a wafer substrate by forming a low K dielectric (K<3.0) overlying the substrate of the wafer, forming an organic silicon-oxide glue layer overlying the low K dielectric, and forming a CMP stop layer dielectric overlying the glue layer dielectric. A void is then formed in the ILD, a conductive material is deposited to fill the void, and a polish process removes the excess conductive material. Forming the glue layer dielectric and the CMP stop layer dielectric is achieved by forming a CVD plasma using an organic precursor and an oxygen precursor and maintaining the plasma through the formation of the glue layer dielectric and the stop layer. The flow rate of the organic precursor is reduced relative to the oxygen precursor flow rate to form a CMP stop layer that is substantially free of carbon.
-
Citations
20 Claims
-
1. A semiconductor fabrication process, comprising:
-
forming an interlevel dielectric (ILD) overlying a substrate of a semiconductor wafer wherein forming the ILD comprises;
forming a low K dielectric overlying a semiconductor substrate of the wafer, wherein a dielectric constant of the low K dielectric is less than or equal to 3.0;
forming an organic, silicon-oxide, glue layer dielectric overlying the low K dielectric; and
forming a CMP stop layer dielectric overlying the glue layer dielectric;
forming a void in the ILD;
depositing a conductive material over the wafer to fill the void; and
removing portions of the conductive material exterior to the void by polishing the wafer with a CMP process and terminating the CMP process on the CMP stop layer dielectric. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method of forming an interlevel dielectric layer (ILD) overlying a substrate of a semiconductor wafer, comprising:
-
forming a first dielectric having a dielectric constant less than or equal to 3.0 overlying the substrate;
depositing, with a chemical vapor deposition process, second and third dielectrics overlying the first dielectric, wherein forming the second and third dielectrics comprises forming a plasma from an oxygen bearing precursor and an organic precursor, maintaining the flow rates of the precursors at first flow rates while forming the second dielectric, and thereafter, reducing the relative flow rate of the organic precursor while maintaining the plasma to form the third dielectric. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A semiconductor fabrication process, comprising:
-
forming a first dielectric having a dielectric constant of less than or equal to 3.0 over a semiconductor substrate;
forming, in a chemical vapor deposition (CVD) reactor chamber using a continuously maintained plasma derived from an oxygen precursor and an organic precursor, a second dielectric overlying the first dielectric and a third dielectric overlying the second dielectric, wherein the second dielectric comprises an organic silicon-oxide and the third dielectric comprises a substantially carbon free silicon-oxide. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification