Direct memory access controller system with message-based programming

• US 20050165980A1
• Filed: 03/23/2005
• Published: 07/28/2005
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Design & Manufacturing Corp. (Broadcom, Inc.)
• Inventors: Wood, John Leland, Clayton, Shawn Adam, Willie, Daniel Brian, Fortin, Brian Mark
• Granted Patent: US 8,108,583 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Claims

1-27. -27. (canceled)

28. A message unit comprising a plurality of first in-first-out memory queues, each queue being operable to store a plurality of data transfer request messages from a first bus interface, each data transfer request message comprising a first address of a location in a source memory, a second address of a location in a destination memory, and a length of data to be transferred from the source memory to the destination memory.

29. The message unit of claim 28, comprising a first interface, a second interface, a message module, a random access memory interface and a random access memory.

30. The message unit of claim 29, wherein the random access memory comprises the plurality of first-in-first-out message queues, each queue operable to store data transfer request messages for a memory access channel.

31. A data transfer request message comprising a first address of a location in a source memory, a second address of a location in a destination memory, and a length of data to be transferred from a source memory to a destination memory.

32. The data transfer request message of claim 31, wherein the source memory is an application specific integrated circuit (ASIC) memory, and the destination memory is a host memory.

33. The data transfer request message of claim 31, further comprising an error detection code.

34. The data transfer request message of claim 31, further comprising message information to be copied to a data transfer response message.

35. The data transfer request message of claim 31, further comprising a control flag bit that instructs a controller to send a data transfer response message.

36. The data transfer request message of claim 31, further comprising a client identification.

37. The data transfer request message of claim 31, further comprising an error detection code seed field.

38. The data transfer request message of claim 31, further comprising an error detection code seed pointer.

39-47. -47. (canceled)