Direct memory access controller system with message-based programming
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Abstract
A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.
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Citations
39 Claims
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1-27. -27. (canceled)
- 28. A message unit comprising a plurality of first in-first-out memory queues, each queue being operable to store a plurality of data transfer request messages from a first bus interface, each data transfer request message comprising a first address of a location in a source memory, a second address of a location in a destination memory, and a length of data to be transferred from the source memory to the destination memory.
- 31. A data transfer request message comprising a first address of a location in a source memory, a second address of a location in a destination memory, and a length of data to be transferred from a source memory to a destination memory.
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39-47. -47. (canceled)
Specification