Phototransistor of CMOS image sensor and method for fabricating the same

• US 20060001121A1
• Filed: 07/05/2005
• Published: 01/05/2006
• Est. Priority Date: 07/05/2004
• Status: Active Grant

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: Dongbuanam Semiconductor, Inc. (DB HiTek Co., Ltd.)
• Inventors: Jeon, In Gyun
• Granted Patent: US 7,229,878 B2
• Time in Patent Office: Days
• US Class Current: 257/462
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor are disclosed, in which the phototransistor includes a first conductive type semiconductor substrate; an STI layer on the first conductive type semiconductor substrate, to define an active area and a device isolation area in the first conductive type semiconductor substrate; a second conductive type well in the first conductive type semiconductor substrate; a gate line on the first conductive type semiconductor substrate; an ohmic contact layer in the second conductive type well, wherein the ohmic contact layer is overlapped with the gate line in state of interposing the STI layer therebetween; and a contact to connect the gate line with the ohmic contact layer through the STI layer.

Claims

1. A phototransistor of a CMOS image sensor comprising:

a first conductive type semiconductor substrate;

an STI layer on the first conductive type semiconductor substrate, to define an active area and a device isolation area in the first conductive type semiconductor substrate;

a second conductive type well in the first conductive type semiconductor substrate;

a gate line on the first conductive type semiconductor substrate;

an ohmic contact layer in the second conductive type well, wherein the ohmic contact layer is overlapped with the gate line in state of interposing the STI layer therebetween; and

a contact to connect the gate line with the ohmic contact layer through the STI layer.

2. The phototransistor of claim 1, further comprising source and drain at both sides of the gate line in the second conductive type well.

3. The phototransistor of claim 1, wherein the ohmic contact layer has the highly doped second conductive type.

4. A method for fabricating a phototransistor of a CMOS image sensor comprising:

defining an active area and a device isolation area in a first conductive type semiconductor substrate by forming an STI layer in the first conductive type semiconductor substrate;

forming a second conductive type well in the first conductive type semiconductor substrate;

forming a gate oxide layer on an entire surface of the first conductive type semiconductor substrate;

forming a contact hole for exposing the predetermined portion of the second conductive type well below the STI layer by selectively removing the gate oxide layer and the STI layer;

forming an ohmic contact layer in the second conductive well below the contact hole;

forming a contact by filling the contact hole with a conductive material; and

forming a gate line on the first conductive type semiconductor substrate including the contact.

5. The method of claim 4, further comprising:

forming source and drain at both sides of the gate line in the second conductive type well by implanting highly doped first conductive type impurity ions to the first conductive type semiconductor substrate in state of using the gate line as a mask, after forming the gate line.

6. The method of claim 4, wherein the ohmic contact layer is formed by implanting highly doped second conductive type impurity ions to the first conductive type semiconductor substrate in state of using the gate oxide layer as a mask.

7. The method of claim 4, wherein a polysilicon is coated on the entire surface of the first conductive type semiconductor substrate including the contact hole, and is then patterned to remain on the predetermined portions for the contact hole and the gate line, so as to form the contact hole and the gate line at the same time.