Data path having grounded precharge operation and test compression capability
First Claim
1. A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier, the data path comprising:
- a pair of global input/output (GIO) signal lines coupled to an input of the IO line sense amplifier;
a pair of local input/output (LIO) signal lines having coupled to a column of memory including the memory cell during a memory read or write operation;
an IO line coupling circuit coupled to the GIO and LIO signal lines, the coupling circuit operable for the memory read operation to couple and decouple each of the GIO signal lines to and from a voltage supply in accordance with voltage levels of the LIO signal lines and further operable for the memory write operation to couple and decouple each of the GIO signal lines to and from a respective one of the LIO signal lines; and
a first precharge circuit coupled to the GIO signal lines and operable to couple the GIO signal lines to ground to precharge the signal lines prior to a memory read or write operation.
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Accused Products
Abstract
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.
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Citations
48 Claims
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1. A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier, the data path comprising:
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a pair of global input/output (GIO) signal lines coupled to an input of the IO line sense amplifier;
a pair of local input/output (LIO) signal lines having coupled to a column of memory including the memory cell during a memory read or write operation;
an IO line coupling circuit coupled to the GIO and LIO signal lines, the coupling circuit operable for the memory read operation to couple and decouple each of the GIO signal lines to and from a voltage supply in accordance with voltage levels of the LIO signal lines and further operable for the memory write operation to couple and decouple each of the GIO signal lines to and from a respective one of the LIO signal lines; and
a first precharge circuit coupled to the GIO signal lines and operable to couple the GIO signal lines to ground to precharge the signal lines prior to a memory read or write operation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A data path for coupling data between a memory cell and an input/output (IO) sense amplifier, the data path comprising:
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a first pair of data signal lines coupled to a first column of memory including a first memory cell during a memory read operation to the first memory cell;
a second pair of data signal lines coupled to a second column of memory including a second memory cell during a memory read operation to the second memory cell;
a third pair of data signal lines coupled to an input of the IO line sense amplifier;
first and second IO line coupling circuits coupled to the first and second data signal lines, respectively, each coupling circuit further coupled to the third pair of data signal lines and operable for a memory read operation to couple and decouple each of the signal lines of the third pair to and from a voltage supply in accordance with voltage levels of the signal lines of the first pair or the voltage levels of the signal lines of the second pair, the first and second coupling circuits operable in a test mode to couple and decouple each of the signal lines of the third pair to and from the voltage supply in accordance with voltage levels of the signal lines of the first pair and the signal lines of the second pair; and
a test compression circuit coupled to the third pair of data signal lines operable in the test mode to compare voltage levels of each of the signal lines to a reference voltage and in response, generate an output test signal indicative of whether the voltage levels of the signal lines of the third pair relative to the reference voltage are complementary or the same. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A memory device, comprising:
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an address bus;
a control bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder and control circuit a read/write circuit coupled to the memory-cell array;
an output data buffer; and
a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) line sense amplifier, the data path comprising;
a pair of global input/output (GIO) signal lines coupled to an input of the IO line sense amplifier;
a pair of local input/output (LIO) signal lines having coupled to a column of memory including the memory cell during a memory read or write operation;
an IO line coupling circuit coupled to the GIO and LIO signal lines, the coupling circuit operable for the memory read operation to couple and decouple each of the GIO signal lines to and from a voltage supply in accordance with voltage levels of the LIO signal lines and further operable for the memory write operation to couple and decouple each of the GIO signal lines to and from a respective one of the LIO signal lines; and
a first precharge circuit coupled to the GIO signal lines and operable to couple the GIO signal lines to ground to precharge the signal lines prior to a memory read or write operation. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A memory device, comprising:
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an address bus;
a control bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder and control circuit a read/write circuit coupled to the memory-cell array;
an output data buffer; and
a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) sense amplifier, the data path comprising;
a first pair of data signal lines coupled to a first column of memory including a first memory cell during a memory read operation to the first memory cell;
a second pair of data signal lines coupled to a second column of memory including a second memory cell during a memory read operation to the second memory cell;
a third pair of data signal lines coupled to an input of the IO line sense amplifier;
first and second IO line coupling circuits coupled to the first and second data signal lines, respectively, each coupling circuit further coupled to the third pair of data signal lines and operable for a memory read operation to couple and decouple each of the signal lines of the third pair to and from a voltage supply in accordance with voltage levels of the signal lines of the first pair or the voltage levels of the signal lines of the second pair, the first and second coupling circuits operable in a test mode to couple and decouple each of the signal lines of the third pair to and from the voltage supply in accordance with voltage levels of the signal lines of the first pair and the signal lines of the second pair; and
a test compression circuit coupled to the third pair of data signal lines operable in the test mode to compare voltage levels of each of the signal lines to a reference voltage and in response, generate an output test signal indicative of whether the voltage levels of the signal lines of the third pair relative to the reference voltage are complementary or the same. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A processor-based system, comprising:
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a data input device;
a data output device;
a processor coupled to the data input and output devices; and
a memory device coupled to the processor, the memory device comprising;
an address bus;
a control bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder and control circuit a read/write circuit coupled to the memory-cell array;
an output data buffer; and
a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) line sense amplifier, the data path comprising;
a pair of global input/output (GIO) signal lines coupled to an input of the IO line sense amplifier;
a pair of local input/output (LIO) signal lines having coupled to a column of memory including the memory cell during a memory read or write operation;
an IO line coupling circuit coupled to the GIO and LIO signal lines, the coupling circuit operable for the memory read operation to couple and decouple each of the GIO signal lines to and from a voltage supply in accordance with voltage levels of the LIO signal lines and further operable for the memory write operation to couple and decouple each of the GIO signal lines to and from a respective one of the LIO signal lines; and
a first precharge circuit coupled to the GIO signal lines and operable to couple the GIO signal lines to ground to precharge the signal lines prior to a memory read or write operation. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A processor-based system, comprising:
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a data input device;
a data output device;
a processor coupled to the data input and output devices; and
a memory device coupled to the processor, the memory device comprising;
an address bus;
a control bus;
an address decoder coupled to the address bus;
a control circuit coupled to the control bus;
a memory-cell array coupled to the address decoder and control circuit a read/write circuit coupled to the memory-cell array;
an output data buffer; and
a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) sense amplifier, the data path comprising;
a first pair of data signal lines coupled to a first column of memory including a first memory cell during a memory read operation to the first memory cell;
a second pair of data signal lines coupled to a second column of memory including a second memory cell during a memory read operation to the second memory cell;
a third pair of data signal lines coupled to an input of the IO line sense amplifier;
first and second IO line coupling circuits coupled to the first and second data signal lines, respectively, each coupling circuit further coupled to the third pair of data signal lines and operable for a memory read operation to couple and decouple each of the signal lines of the third pair to and from a voltage supply in accordance with voltage levels of the signal lines of the first pair or the voltage levels of the signal lines of the second pair, the first and second coupling circuits operable in a test mode to couple and decouple each of the signal lines of the third pair to and from the voltage supply in accordance with voltage levels of the signal lines of the first pair and the signal lines of the second pair; and
a test compression circuit coupled to the third pair of data signal lines operable in the test mode to compare voltage levels of each of the signal lines to a reference voltage and in response, generate an output test signal indicative of whether the voltage levels of the signal lines of the third pair relative to the reference voltage are complementary or the same. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42)
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43. A method for coupling data between a memory cell in a memory array to and from an input/output sense amplifier, the method comprising:
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precharging a pair of global data lines to ground;
in the event of a read operation, coupling the global data lines to a voltage supply, coupling the data from the memory cell and complementary data to a pair of local data lines, and decoupling one of the global data lines from the voltage supply based on the data and its complement coupled to the local data lines; and
in the event of a write operation, coupling the memory cell to the pair of local data lines, coupling each of the global data signal lines to a respective one of the local data lines, and coupling complementary data representing the data to be written to the memory cell to the global data signal lines. - View Dependent Claims (44, 45)
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46. A method for testing memory cells of a memory array, comprising:
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coupling a pair of global data signal lines to a voltage supply through a plurality of switches;
coupling data of a plurality of memory cells to a respective one of a plurality of local data signal lines, the local data signal lines coupled to a respective one of the plurality of switches;
for each of the plurality of local data signal lines, decoupling one of the pair of global data signal lines from the voltage supply based on the data of the respective memory cell coupled to the respective local data signal lines;
comparing the voltage levels of each global data signal line to a reference voltage; and
generating an output signal having a logic level indicative of whether the data coupled to the respective local data signal lines matches expected data based on whether the voltage level of each global data signal line relative to the reference voltage is the same or different. - View Dependent Claims (47, 48)
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Specification