Semiconductor structures and memory device constructions
8 Assignments
0 Petitions
Accused Products
Abstract
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
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Citations
102 Claims
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1-53. -53. (canceled)
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54. A semiconductor structure, comprising:
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a semiconductor substrate;
a nitride-containing material lattice over the substrate; and
an array of non-nitride regions spaced from one another by segments of the lattice;
the array having a defined first pitch along a first axis and a defined second pitch along a second axis substantially orthogonal to the first axis;
the second pitch being about twice as big as the first pitch. - View Dependent Claims (55, 58)
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56-57. -57. (canceled)
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59-60. -60. (canceled)
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61. A semiconductor structure, comprising:
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a semiconductor substrate;
a gateline lattice over the substrate; and
an array of non-gateline regions spaced from one another by segments of the lattice;
the array having a defined first pitch along a first axis and a defined second pitch along a second axis substantially orthogonal to the first axis;
the second pitch being about twice as big as the first pitch;
the non-gateline regions comprising elevationally-elongated source/drain regions;
the gateline lattice and source/drain regions together forming a plurality of transistor constructions in which pairs of the source/drain regions are gatedly connected to one other through the gateline lattice. - View Dependent Claims (62, 64, 67, 70, 73, 74, 75)
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63. (canceled)
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65-66. -66. (canceled)
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68-69. -69. (canceled)
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71-72. -72. (canceled)
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76. A memory device construction, comprising:
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a semiconductor substrate;
a gateline over the substrate;
a pair of elevationally-elongated source/drain regions over the substrate and at least partially surrounded by the gateline, one of the source/drain regions being a first source/drain region and consisting essentially of conductively-doped epitaxial silicon, the other source/drain region being a second source/drain region and consisting essentially of conductively-doped silicon which is not epitaxial, the first and second source/drain regions being gatedly connected to one another through the gateline;
a memory storage device electrically connected to either the first source/drain region or the second source/drain region; and
a digit line electrically connected to whichever of the first and second source/drain regions is not electrically connected to the memory storage device. - View Dependent Claims (77, 78, 79, 80, 81, 82, 83, 84, 85)
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86. (canceled)
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87. A memory device construction, comprising:
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a semiconductor substrate;
a gateline over the substrate;
a pair of elevationally-elongated source/drain regions over the substrate and at least partially surrounded by the gateline, one of the source/drain regions being a first source/drain region and the other source/drain region being a second source/drain region;
a memory storage device electrically connected to said first source/drain region;
a digit line electrically connected to said second source/drain region; and
wherein;
the first source/drain region consists essentially of a first conductively-doped semiconductor material having an uppermost region doped to a first conductivity type and a remainder doped to a second conductivity type opposite the first conductivity type;
the first source/drain region consists essentially of a second conductively-doped semiconductor material having an uppermost region doped to the first conductivity type, and a remainder doped to the second conductivity type; and
the substrate comprises a segment extending between the first and second source/drain regions and doped to the second conductivity type. - View Dependent Claims (88, 89, 90, 91, 92, 93, 94)
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95. (canceled)
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96. A memory device construction, comprising:
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a semiconductor substrate;
a gateline over the substrate;
a pair of elevationally-elongated source/drain regions over the substrate and at least partially surrounded by the gateline, one of the source/drain regions being a first source/drain region and the other source/drain region being a second source/drain region;
a memory storage device electrically connected to said first source/drain region;
a digit line electrically connected to said second source/drain region; and
wherein;
the first source/drain region consists essentially of a first conductively-doped semiconductor material having an uppermost region doped to n+, and a remainder doped to n−
;
the second source/drain region consists essentially of a second conductively-doped semiconductor material having an uppermost region doped to n+, and a remainder doped to p; and
the substrate comprises;
a first conductively-doped diffusion region ohmically connected to the first source/drain region and doped to n−
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a second conductively-doped diffusion region ohmically connected to the second source/drain region and doped to p−
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a segment extending from the first conductively-doped diffusion region to the second conductively-doped diffusion region and doped to p−
. - View Dependent Claims (97, 98, 99, 100, 101)
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102. (canceled)
Specification