Wiring structure to minimize stress induced void formation

• US 20060019414A1
• Filed: 07/26/2004
• Published: 01/26/2006
• Est. Priority Date: 07/26/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chien-Jung, Chen, Hsueh-Chung, Hu, Ding-Da, Fan, Su-Chen
• Granted Patent: US 7,301,239 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.

Claims

1. A wiring structure connecting a metal feature having a length, width, and thickness to a via for minimizing stress induced void formation, comprising:

a plurality of “

n”

overlapping segments each comprised of two ends and having a width, a length, and a thickness wherein one end of a first segment is connected to the metal feature and one end of the nth segment is connected to the via and wherein an end of a segment and an end of an adjacent segment form a bend at an angle θ and

a plurality of segments form at least one bending portion.

2. The wiring structure of claim 1 wherein the metal layer, “

n”

overlapping segments, and via are comprised of copper.

3. The wiring structure of claim 1 wherein the first segment is formed along a first axis and the nth segment is formed along the first axis or along an axis that is parallel to the first axis and the bending portion is not aligned along the first axis.

4. The wiring structure of claim 1 wherein the width of a segment is less than the width or length of the metal feature.

5. The wiring structure of claim 1 wherein the combined length of the “

n”

segments is greater than about 10 microns.

6. The wiring structure of claim 1 wherein the angle θ

is between about 45° and

135°

.

7. The wiring structure of claim 1 further comprising at least one extension formed on one end of a segment and substantially aligned along the same axis as formed by the two ends of the segment.

8. A via test structure formed on a semiconductor substrate comprising:

(a) a first metal layer comprising a first metal line and second metal line which are each comprised of a first segment, a middle segment, and a third segment wherein the first and third segments have a length, width, and thickness and the middle segment has a plurality of “

n”

overlapping subsegments each having a width, length, thickness, and two ends, wherein one end of a first subsegment is connected to a first segment and one end of the nth subsegment is connected to a third segment and wherein an end of a subsegment and an end of an adjacent subsegment form a bend at an angle θ and

said middle segment is comprised of at least one bending portion;

(b) a second metal layer comprising a first metal line and second metal line which are each comprised of a first segment, a middle segment, and a third segment wherein the first and third segments have a length, width, and thickness and the middle segment has a plurality of “

n”

overlapping subsegments each having a width, length, two ends, and thickness wherein one end of a first subsegment connects to a first segment and one end of the nth subsegment connects to a third segment and wherein an end of a subsegment and an end of an adjacent subsegment form a bend at an angle θ and

said middle segment is comprised of at least one bending portion;

(c) a via formed between a first segment in the first metal layer and a first segment in the second metal layer;

(d) first and second bonding pads in the first metal layer that connect to a third segment in the first and second metal lines, respectively, in the first metal layer; and

(e) first and second bonding pads in the second metal layer that are connected to a third segment of the first and second metal lines, respectively, in the second metal layer.

9. The via test structure of claim 8 wherein the first and second metal layers and the via are comprised of copper.

10. The via test structure of claim 8 wherein the first segment, the first subsegment, the nth subsegment, and the third segment in the first metal line of the first metal layer are formed along a first axis.

11. The via test structure of claim 10 wherein the first segment, the first subsegment, the nth subsegment, and the third segment in the second metal line of the first metal layer are formed along a second axis that is perpendicular to said first axis.

12. The via test structure of claim 10 wherein the first segment, the first subsegment, the nth subsegment, and the third segment in the first metal line of the second metal layer are formed along a third axis that is parallel to said first axis.

13. The via test structure of claim 12 wherein the first segment, the first subsegment, the nth subsegment, and the third segment in the second metal line of the second metal layer are formed along a fourth axis that is perpendicular to said third axis.

14. The via test structure of claim 8 wherein the width of a subsegment is less than the width of a first segment or third segment.

15. The via test structure of claim 8 wherein the thickness of a subsegment is equal to the thickness of a first segment or a third segment.

16. The via test structure of claim 8 wherein the combined length of the “

n”

subsegments is greater than about 10 microns.

17. The via test structure of claim 8 wherein the angle θ

is between about 45° and

135°

.

18. The via test structure of claim 8 wherein the first segments of the first and second metal lines in the first metal layer are the same segment which is connected to the bottom of said via.

19. The via test structure of claim 8 wherein the first segments of the first and second metal lines in the second metal layer are the same segment which is connected to the top of said via.

20. The via test structure of claim 8 wherein a bending portion is comprised of a plurality of subsegments that are not aligned along a first, second, third, or fourth axis.

21. A method of determining via resistance during a reliability stress test in a test structure that includes a first metal layer connected to the bottom of a via and a second metal layer connected to the top of the via, comprising:

(a) applying a current to a first bonding pad in a first metal layer formed on a substrate, said first bonding pad being connected to the bottom of a via by a first metal line comprised of two ends and a segment that has a serpentine pattern;

(b) measuring the voltage at a second bonding pad in said first metal layer, said second bonding pad being connected to the bottom of said via by a second metal line comprised of two ends and a segment that has a serpentine pattern;

(c) measuring the voltage of a first bonding pad in a second metal layer formed above said first metal layer on said substrate, said first bonding pad in said second metal layer being connected to the top of said via by a first metal line comprised of a segment that has two ends and a serpentine pattern; and

(d) connecting a second bonding pad in said second metal layer to a predetermined voltage potential, said second bonding pad in said second metal layer being connected to the top of said via by a second metal line that has two ends and a segment with a serpentine pattern.

22. The method of claim 21 wherein said predetermined voltage potential is ground potential.

23. The method of claim 21 wherein said serpentine pattern is comprised of a plurality of “

n”

overlapping subsegments each having a width, length, thickness, and two ends wherein one end of a first subsegment is connected to an end of a metal line attached to the via and one end of the nth subsegment is connected to the other end of the metal line attached to a bonding pad and wherein an end of one subsegment and an end of an adjacent subsegment form a bend at an angle θ and

said serpentine pattern is comprised of at least one bending portion.

24. The method of claim 21 wherein the first and second metal layers and the via are substantially comprised of copper.

25. The method of claim 23 wherein the width of a subsegment is less than the width of an end of a first metal line or second metal line.

26. The method of claim 21 wherein the angle 0 is between about 45°

and 135°

.

27. The method of claim 21 wherein the reliability stress test is further comprised of heating said substrate for a predetermined period of time (t) and then remeasuring said via resistance by repeating steps (a) through (d) in which the applied current amplitude is I_T, said voltage at the second bonding pad in the first metal layer has an amplitude V_IT, and said voltage at the first bonding pad in said second metal layer has an amplitude V_2T, and the via resistance is determined by dividing (V_IT−

V_2T) by I_T.

28. An interconnect structure to reduce stress induced void formation, comprising:

(a) a first conducting layer including a large area portion having a first width, a first length, and a first thickness, an enlongated protrusion having a second width and length, first thickness, and two ends, wherein one end is connected to the large area portion and the other end is connected to a via and said protrusion is comprised of at least one bending portion;

(b) a via connected at a first end to the protrusion in the first conducting layer and at a second end to a second conducting layer.

29. The interconnect structure of claim 28 wherein said protrusion is comprised of a plurality of “

n”

overlapping segments and a bending portion that includes a plurality of segments in which an end of one segment and an end of an adjacent segment overlap to form a bend at an angle θ

.

30. The interconnect structure of claim 29 wherein the angle θ

is between about 45° and

135°

.

31. The interconnect structure of claim 28 wherein the bending portion has the shape of an arc.

32. The interconnect structure of claim 28 wherein the first conducting layer, second conducting layer, protrusion, and the via are comprised of a metal.

33. The interconnect structure of claim 32 wherein said metal is copper.

34. The interconnect structure of claim 28 wherein the first thickness of the first conducting layer is between about 0.2 and 1 microns, the height of the via is about 0.2 to 1 microns, and wherein the second conducting layer has a thickness of about 0.2 to 1 microns.

35. The interconnect structure of claim 28 wherein the combined length of the “

n”

segments in the protrusion is greater than about 10 microns and the second width of a segment is between about 0.1 and 10 microns.

36. The interconnect structure of claim 28 wherein the first segment is formed along a first axis and the nth segment is formed along the first axis or along an axis that is parallel to the first axis.

37. The interconnect structure of claim 28 wherein the via is formed on the “

nth”

segment at a distance of about 0.1 and 10 microns from the end of the nth segment that does not overlap with the (n−

1)th segment.

38. The interconnect structure of claim 28 wherein the width of said via is less than the second width of said nth segment and the height of the via is between about 0.2 and 10 microns.

39. The interconnect structure of claim 29 further comprised of at least one extension at the end of a segment adjacent to a bend.

40. The interconnect structure of claim 39 wherein said extension has a second width, a length of about 0.01 to 1 microns, a first thickness, and is comprised of the same conducting material as in the first conducting layer.

41. An interconnect structure to reduce stress induced void formation, comprising:

(a) a first conducting layer having a first width, a first length, a first thickness, and sides; and

(b) a protrusion on one side of the first conducting layer, said protrusion having a second width, a second length, a first thickness, and two ends formed along a first axis, wherein said protrusion has at least one bending portion comprised of a plurality of overlapping segments each with two ends that are not aligned along said first axis and wherein said bending portion includes at least one extension formed at the end of a segment.

42. The interconnect structure of claim 41 further comprising:

a via connected at a first end to the protrusion and at a second end to a second conducting layer.

43. The interconnect structure of claim 42 wherein the first conducting layer, second conducting layer, the via, and the protrusion are substantially comprised of a metal.

44. The interconnect structure of claim 43 wherein said metal is copper.

45. The interconnect structure of claim 41 wherein the end of the protrusion on the side of the first conducting layer is a first segment and the second end of the protrusion is the nth segment in a plurality of “

n”

overlapping segments each having a length, a second width, and a first thickness.

46. The interconnect structure of claim 45 wherein one segment and an adjacent segment overlap to form a bend at an angle θ

.

47. The interconnect structure of claim 46 wherein the angle θ

is between about 45° and

135°

.

48. The interconnect structure of claim 45 wherein combined length of the “

n”

overlapping segments is greater than about 10 microns.

49. The interconnect structure of claim 41 wherein said extension has a width of about 0.01 to 1 microns and a length of about 0.5 to 50 microns.

50. A method of forming an interconnect having increased resistance to void formation, said interconnect being formed on a substrate, comprising:

(a) providing a substrate with a first dielectric layer formed thereon;

(b) forming an opening in said first dielectric layer and depositing a first conducting layer that fills said opening, said first conducting layer being comprised of a large area portion having a first length, a first width, a first thickness, and sides, and a protrusion with a first thickness, a second length, and a second width, said protrusion having two ends wherein one end is connected to a side of the large area portion and the other end is connected to a via and wherein said protrusion has at least one bending portion and a plurality of “

n”

overlapping segments each with two ends;

(c) depositing a second dielectric layer over said first dielectric layer and said first conducting layer; and

(d) forming a second opening comprised of a via opening substantially aligned with the nth segment in said protrusion and an overlying trench opening in said second dielectric layer and depositing a second conducting layer that fills said second opening.

51. The method of claim 50 further comprising forming an etch stop layer prior to depositing the second dielectric layer, the etch stop layer being comprised of a material selected from the group consisting essentially of SiO₂, fluorine doped SiO₂, carbon doped SiO₂, a silsesquioxane, a polyarylether, benzocyclobutene, a polyimide, and combinations thereof.

52. The method of claim 50 wherein the first and second conducting layers are substantially comprised of copper.

53. The method of claim 50 wherein the first thickness of the first conducting layer is between about 0.2 and 1 microns, the height of the via is between about 0.2 and 1 microns, and wherein the second conducting layer has a thickness of between about 0.2 and 1 microns.

54. The method of claim 50 wherein said second length is less than the first length and the second width is less than the first width.

55. The method of claim 50 wherein the protrusion has a second length of greater than 10 microns and a second width of between 0.1 and 10 microns.

56. The method of claim 50 wherein an end of a segment and an end of an adjacent segment overlap to form a bend at an angle between about 45°

and 135°

.

57. The method of claim 50 wherein the width of said via is less than the second width of said protrusion.

58. The method of claim 56 wherein said protrusion is further comprised of at least one extension on the end of one of the segments beyond a bend and along an axis formed by the two ends of the segment.

59. The method of claim 58 wherein said extension has a second width, a length of between about 0.01 to 1 microns, and a first thickness.