Semiconductor chip having gettering layer, and method for manufacturing the same

• US 20060022321A1
• Filed: 07/27/2005
• Published: 02/02/2006
• Est. Priority Date: 07/28/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Koga, Tsuyoshi, Shibata, Jun, Tobimatsu, Hiroshi, Nishida, Akio, Higashide, Yoshiko, Matsukawa, Kazuhito
• Granted Patent: US 7,582,950 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Claims

1. A semiconductor chip wherein an element layer is formed on the front face, and the back face is joined to an underlying member, wherein a gettering layer is formed on said back face.

2. The semiconductor chip according to claim 1, wherein the thickness of said semiconductor chip is 100 μ

m or less.

3. The semiconductor chip according to claim 1, wherein said gettering layer is a damaged layer.

4. The semiconductor chip according to claim 1, wherein said gettering layer is a thin film consisting of a polycrystalline silicon film or a silicon nitride film.

5. The semiconductor chip according to claim 4, wherein the thickness of said thin film is 0.5 to 1.5 μ

m.

6. The semiconductor chip according to claim 1, wherein said semiconductor chip contains a crystal lattice defect layer, and the density of crystal lattice defects contained in the entire semiconductor chip is 1×

10⁴/cm² or more.

7. A semiconductor package fabricated by laminating a plurality of semiconductor chips on a substrate, wherein said semiconductor chips are laminated so that the thickness of said semiconductor chip is relatively thicker than the thickness of a semiconductor chip laminated immediately above said semiconductor chip.

8. The semiconductor package according to claim 7, wherein a silicon substrate or a polycrystalline silicon film is laminated as a cushioning material between said plurality of semiconductor chips.

9. A method for manufacturing a semiconductor chip, wherein a gettering layer for trapping heavy metals is formed on the back face after cutting out of a wafer by dicing.

10. The method for manufacturing a semiconductor chip according to claim 9, wherein said gettering layer is formed by mechanically grinding using a silica material.

11. The method for manufacturing a semiconductor chip according to claim 9, wherein said gettering layer is formed by grinding using a grinding machine.

12. The method for manufacturing a semiconductor chip according to claim 9, wherein said gettering layer is formed by implanting ions.

13. The method for manufacturing a semiconductor chip according to claim 9, wherein said gettering layer is formed by a thin film consisting of a polycrystalline silicon film or a silicon nitride film.

14. The method for manufacturing a semiconductor chip according to claim 9 comprising:

a step for forming a crystal lattice defect layer in said wafer before said dicing so that the density of crystal lattice defects in said wafer is 1×

10⁴/cm² or more; and

a step for forming a semiconductor chip by said dicing said wafer so that the density of crystal lattice defects is 1×

10⁴/cm² or more.