Structured integrated circuit device

• US 20060028241A1
• Filed: 07/22/2005
• Published: 02/09/2006
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi, Apostol, Adrian, Levinthal, Adam, Zeman, Richard, Iacobut, Romeo, Grigore, George C., Wurman, Ze'ev, Avram, Petrica, Kapel, Alon
• Granted Patent: US 7,157,937 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Claims

1. A semiconductor device comprising:

a multiplicity of logic blocks, and

metal and via connection layers overlying the multiplicity of logic blocks for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;

wherein said logic blocks include

a logic array, said logic array including a multiplicity of logic cells, and at least one of;

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer; and

a configurable RAM block, and wherein said RAM block configuration is customized by said custom via layer.

2. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising a look-up table, another logic element, and a multiplicity of inverters of various sizes selectively connected to said logic element within said logic cell to change the drive strength of said logic cell'"'"'s output;

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer,

said logic array further comprising a configurable RAM block, and wherein a configuration of said RAM block is customized by said custom via layer.

3. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one inverter, at least one NAND function, and a look-up table,

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer, and wherein

said customized interconnection provides a connection between said at least one NAND function and said at least one inverter.

4. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said metal and via connection layers comprise long and short metal segments, said long metal segments comprising metal segments connected to jumpers to periodically change tracks.

5. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up table;

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof,

wherein the number of said metal and via connection layers is determined by the customized interconnect requirements of at least one design.

6. The semiconductor wafer comprising at least two semiconductor devices according to claim 5, wherein one or more designs are selected for the at least two semiconductor devices to require a common number of said multiplicity of metal and via connection layers for all of said semiconductor devices.

7. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells,

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer; and

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer, and wherein said I/O cells comprise at least three rows of pads.

8. The semiconductor device according to claim 7, wherein at least one row of pads is dedicated to provide at least one power connection to said logic array.

9. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells,

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer; and

a customizable clock distribution structure, wherein said customizable clock distribution structure comprises at least one of the components selected from the group consisting of;

a customizable trimmer cell to fine tune said clock distribution structure'"'"'s delay, wherein said customizable trimmer cell is customized by said custom via layer; and

customizable connections to a phase lock loop circuit, wherein said customizable connections determine the phase and frequency of each clock.

10. A semiconductor device comprising:

a multiplicity of wire segments on a single layer of metal serially connecting a group of probe pads and a group of logic arrays, each of said logic arrays including;

a multiplicity of logic cells, each logic cell comprising at least one look-up table;

metal connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof;

a configurable ROM block; and

a built-in microprocessor, having the ability to perform testing of said logic array.

11. A semiconductor wafer comprising a multiplicity of reticle images, said reticle images further comprising a multiplicity of dies, and one or more metal interconnects between said dies, wherein

all of said multiplicity of dies are tested with a single probe of each of said reticle images.

12. The semiconductor wafer according to claim 11, wherein said multiplicity of dies includes a ring oscillator to use in performance measurements.

13. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up table,

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer

wherein said at least one look up table is permanently customized by the placement of vias on a single via layer other than said single custom via layer.

14. A logic array comprising:

a multiplicity of identical logic cells, each identical logic cell comprising at least one look-up table,

metal connection layers overlying the multiplicity of identical logic cells for providing at least one permanent customized direct interconnect between various inputs and outputs thereof,

wherein the functionality of each of said multiplicity of identical logic cells is one of a number of functions determined by a configuration of said look-up tables.