Apparatus and methods for communicating with programmable logic devices

• US 20060038586A1
• Filed: 06/10/2003
• Published: 02/23/2006
• Est. Priority Date: 06/10/2003
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Duwel, Keith, Veenstra, Kerry, Prasad, Nitin, Joyce, Juju Chacko, Xia, Renxin
• Granted Patent: US 7,356,620 B2
• Time in Patent Office: Days
• US Class Current: 326/39
• CPC Class Codes: G06F 13/10 Program control for peripheral devices G06F13/14 - G06F13/42 take precedence
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Claims

1. A circuit arrangement, comprising:

a programmable logic device (PLD); and

a storage device, the storage device adapted to communicate information with the programmable logic device, the storage device further adapted to communicate with the programmable logic device via a bi-directional interface.

2. The circuit arrangement according to claim 1, wherein the storage device is further adapted to provide configuration information to the programmable logic device.

3. The circuit arrangement according to claim 2, wherein the bi-directional interface comprises a serial interface.

4. The circuit arrangement according to claim 3, wherein the storage device is further adapted to communicate via the serial interface.

5. The circuit arrangement according to claim 4, wherein the storage device comprises a FLASH memory.

6. The circuit arrangement according to claim 5, wherein the serial interface comprises:

a serial data in signal;

a serial data out signal;

a clock signal;

a chip enable signal; and

a handshaking signal.

7. The circuit arrangement according to claim 6, wherein the programmable logic device provides the clock signal and an operation code to the FLASH memory, and wherein the FLASH memory provides the configuration information to the programmable logic device in response to the clock signal and the operation code.

8. The circuit arrangement according to claim 2, wherein the bi-directional interface comprises a parallel interface.

9. The circuit arrangement according to claim 8, wherein the storage device is further adapted to communicate via the parallel interface.

10. The circuit arrangement according to claim 9, wherein the storage device comprises a FLASH memory.

11. The circuit arrangement according to claim 10, wherein the parallel interface comprises:

a set of data signals;

a set of address signals;

a write enable signal;

an output enable signal; and

a chip enable signal.

12. The circuit arrangement according to claim 2, wherein the programmable logic device uses the storage device to store and retrieve information via the bi-directional interface.

13. The circuit arrangement according to claim 12, wherein an external device uses the storage device to store and retrieve information via the bi-directional interface.

14. The circuit arrangement according to claim 2, used in a data-processing system.

15. The circuit arrangement according to claim 2, used in a data-processing system that includes a processor implemented in the programmable logic device.

16. The circuit arrangement according to claim 2, used in a data-processing system that includes a processor coupled to the programmable logic device.

17. The circuit arrangement according to claim 1, further comprising a coupler, the coupler adapted to be selectably coupled to the bi-directional interface.

18. The circuit arrangement according to claim 17, wherein the programmable logic device couples to the bi-directional interface via a coupling device adapted to be selectably de-activated.

19. The circuit arrangement according to claim 18, wherein the coupling device is adapted to be de-activated when the coupler is coupled to the bi-directional interface.

20. The circuit arrangement according to claim 19, further comprising an external device adapted to couple to the bi-directional interface via the coupler.

21. The circuit arrangement according to claim 20, wherein the external device is further adapted to communicate with the storage device via the bi-directional interface.

22. The circuit arrangement according to claim 21, wherein the external device is further adapted to provide configuration information to the storage device.

23. The circuit arrangement according to claim 22, wherein the bi-directional interface comprises a serial interface.

24. The circuit arrangement according to claim 23, wherein the storage device comprises a FLASH memory.

25. An apparatus, comprising:

a first programmable logic device coupled in a cascade arrangement to a second programmable logic device; and

a storage device, the storage device adapted to communicate with the first and second programmable logic devices, the storage device further configured to communicate with the first programmable logic device via a bi-directional interface.

26. The apparatus according to claim 25, wherein the first programmable logic device is adapted to receive configuration information from the storage device.

27. The apparatus according to claim 26, wherein the bi-directional interface comprises a plurality of interface signals, and wherein the second programmable logic device is adapted to receive configuration information from the storage device via at least some of the interface signals.

28. The apparatus according to claim 27, wherein the second programmable logic device is adapted to receive configuration information from the storage device after the first programmable logic device has finished receiving configuration information from the storage device.

29. The apparatus according to claim 28, wherein the first programmable logic device is adapted to provide a first signal adapted to indicate that the first programmable logic device has finished receiving configuration information from the storage device.

30. The apparatus according to claim 29, wherein the second programmable logic device is adapted to provide a second signal adapted to indicate that the second programmable logic device has finished receiving configuration information from the storage device.

31. The apparatus according to claim 30, wherein the first programmable logic device comprises a master device of the bi-directional interface.

32. The apparatus according to claim 31, wherein the second programmable logic device comprises a slave device of the bi-directional interface.

33. The apparatus according to claim 32, wherein the bi-directional interface comprises a serial interface.

34. The apparatus according to claim 33, wherein the storage device comprises a FLASH memory.

35. The apparatus according to claim 34, wherein the first programmable logic device is adapted:

(a) to provide a clock signal to the FLASH memory and to the second programmable logic device, and (b) to provide at least one operation code to the FLASH memory; and

wherein the FLASH memory is adapted to provide configuration information to the first and second programmable logic devices in response to the clock signal and the at least one operation code.

36. The apparatus according to claim 32, wherein the first programmable logic device is further adapted to generate a first error signal in the event of an error during the reception of configuration information by the first programmable logic device.

37. The apparatus according to claim 36, wherein the second programmable logic device is further adapted to generate a second error signal in the event of an error during the reception of configuration information by the second programmable logic device.

38. The apparatus according to claim 28, further comprising a coupler, the coupler adapted to be selectably coupled to the bi-directional interface.

39. The circuit arrangement according to claim 38, wherein the first programmable logic device is further adapted to couple to the bi-directional interface via a first coupling device adapted to be selectably de-activated, and wherein the second programmable logic device is further adapted to couple to the bi-directional interface via a second coupling device adapted to be selectably de-activated.

40. The circuit arrangement according to claim 39, wherein the first and second coupling devices are adapted to be de-activated when the coupler is coupled to the bi-directional interface.

41. The circuit arrangement according to claim 40, further comprising an external device adapted to couple to the bi-directional interface via the coupler, and wherein the external device is further adapted to provide information to the storage device via the bi-directional interface.

42. The circuit arrangement according to claim 41, wherein the information provided by the external device to the storage device comprises configuration information.

43. A method of communicating information between a programmable logic device (PLD) and a storage device, the method comprising:

providing the programmable logic device;

providing the storage device;

retrieving the information from the storage device; and

communicating the information to the programmable logic device via a bi-directional interface.

44. The method according to claim 43, wherein the information in communicating the information to the programmable logic device via the bi-directional interface comprises configuration information.

45. The method according to claim 44, wherein the interface in communicating the information to the programmable logic device via the bi-directional interface comprises a serial interface.

46. The method according to claim 45, wherein the storage device is further adapted to communicate via the serial interface.

47. The method according to claim 46, wherein the storage device comprises a FLASH memory.

48. The method according to claim 44, wherein the bi-directional interface comprises a parallel interface.

49. The method according to claim 48, wherein the storage device is further adapted to communicate via the parallel interface.

50. The method according to claim 49, wherein the storage device comprises a FLASH memory.

51. The method according to claim 44, further comprising using the programmable logic device to store information in, and retrieve information from, the storage device via the bi-directional interface.

52. The method according to claim 51, further comprising using an external device to store information in, and retrieve information from, the storage device via the bi-directional interface.

53. The method according to claim 43, further comprising de-coupling selectively the programmable logic device couples to the bi-directional interface in response to an external device coupling to the bi-directional interface.

54. The method according to claim 53, further comprising providing information from the external device to the storage device via the bi-directional interface.

55. The method according to claim 54, wherein the information in providing information from the external device to the storage device via the bi-directional interface comprises configuration information.

56. The method according to claim 55, wherein the bi-directional interface comprises a serial interface.

57. The method according to claim 56, wherein the storage device comprises a FLASH memory.

58. A method of communicating information, the method comprising:

providing a first programmable logic device and a second programmable logic device coupled to the first programmable logic device in a cascade arrangement;

providing a storage device;

retrieving the information from the storage device; and

communicating the information to the first programmable logic device via a bi-directional interface.

59. The method according to claim 58, wherein the information in communicating the information to the first programmable logic device via a bi-directional interface comprises configuration information.

60. The method according to claim 59, wherein the bi-directional interface in communicating the information to the first programmable logic device via a bi-directional interface comprises a plurality of interface signals, the method further comprising communicating the configuration information to the second programmable logic device via at least some of the interface signals.

61. The method according to claim 60, wherein communicating the configuration information to the second programmable logic device occurs after communicating the information to the first programmable logic device.

62. The method according to claim 61, further comprising indicating that the first programmable logic device has finished receiving configuration information from the storage device by providing a first signal.

63. The method according to claim 62, further comprising indicating that the second programmable logic device has finished receiving configuration information from the storage device by providing a second signal.

64. The method according to claim 63, further comprising operating the first programmable logic device as a master device of the bi-directional interface.

65. The method according to claim 64, further comprising operating the second programmable logic device as a slave device of the bi-directional interface.

66. The method according to claim 65, wherein the bi-directional interface comprises a serial interface.

67. The method according to claim 66, wherein the storage device comprises a FLASH memory.

68. The method according to claim 65, further comprising:

generating a first error signal in the event of an error during the reception of configuration information by the first programmable logic device; and

generating a second error signal in the event of an error during the reception of configuration information by the second programmable logic device.

69. The method according to claim 65, further comprising using the first programmable logic device to provide a clock signal to the storage device and to the second programmable logic device.