Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method

• US 20060041774A1
• Filed: 08/19/2005
• Published: 02/23/2006
• Est. Priority Date: 08/20/2004
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shimura, Hidekichi
• Granted Patent: US 7,412,679 B2
• Time in Patent Office: Days
• US Class Current: 714/1
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption

Abstract

A low-power-consumption type semiconductor integrated circuit incorporating a variety of functions and a semiconductor integrated circuit manufacturing method are provided. As an example of a semiconductor integrated circuit, a system LSI 1 has first circuit blocks 41 through 48 that do not include a critical path, second circuit blocks 51 through 54 that include a critical path, first power supply wiring 25 that supplies a first power supply to first circuit blocks 41 through 48, and second power supply wiring 26 that supplies a second power supply of higher voltage than the first power supply to second circuit blocks 51 through 54, with second circuit blocks 51 through 54 being connected to second power supply wiring 26 by means of wiring areas 61 through 64 respectively, and being supplied with the second power supply.

Claims

1. A semiconductor integrated circuit comprising:

a first circuit block that does not include a critical path;

a second circuit block that includes said critical path;

first power supply wiring that supplies a first power supply to said first circuit block; and

second power supply wiring that supplies a second power supply of higher voltage than said first power supply to said second circuit block.

2. The semiconductor integrated circuit according to claim 1, wherein:

said first circuit block comprises at least one of a first semiconductor element and a first logic circuit that do not form a critical path;

said second circuit block comprises at least one of a second semiconductor element and a second logic circuit that form said critical path;

said first power supply wiring is connected to either said first semiconductor element or said first logic circuit; and

said second power supply wiring is connected to either said second semiconductor element or said second logic circuit.

3. The semiconductor integrated circuit according to claim 1, further comprising:

a third circuit block that includes said critical path; and

third power supply wiring that supplies a third power supply of higher voltage than said second power supply to said third circuit block.

4. The semiconductor integrated circuit according to claim 2, wherein:

said first circuit block has at least one of said first semiconductor element and said first logic circuit; and

in said second circuit block a threshold voltage value of either said second semiconductor element or said second logic circuit is lower than a threshold voltage of either said first semiconductor element or said first logic circuit.

12. The semiconductor integrated circuit according to claim 2, further comprising:

a third circuit block that includes said critical path; and

third power supply wiring that supplies a third power supply of higher voltage than said second power supply to said third circuit block.

5. A semiconductor integrated circuit comprising:

basic cell rows in which a plurality of circuit blocks are placed, arranged in a plurality in a first direction;

a wiring placement area formed between adjacent said basic cell rows in said first direction;

reference power supply wiring that extends in a second direction in said wiring placement area and supplies a reference power supply to said circuit blocks;

first power supply wiring that extends in said second direction in said wiring placement area and supplies a first power supply of higher voltage than said reference power supply to said circuit blocks; and

second power supply wiring that extends in said second direction in said wiring placement area and supplies a second power supply of higher voltage than said first power supply to said circuit blocks.

6. The semiconductor integrated circuit according to claim 5, further comprising a first circuit block that does not include a critical path and a second circuit block that includes a critical path in said circuit blocks placed in said basic cell row, wherein:

said reference power supply wiring and said first power supply wiring are connected to t said he first circuit block; and

said reference power supply wiring and said second power supply wiring are connected to said second circuit block.

7. The semiconductor integrated circuit according to claim 6, further comprising a level shifter that performs input signal level or output signal level alignment between said first circuit block and said second circuit block.

8. The semiconductor integrated circuit according to claim 5, further comprising third power supply wiring that extends in said second direction in said wiring placement area and supplies a third power supply of higher voltage than said second power supply to said circuit blocks.

13. The semiconductor integrated circuit according to claim 6, further comprising third power supply wiring that extends in said second direction in said wiring placement area and supplies a third power supply of higher voltage than said second power supply to said circuit blocks.

14. The semiconductor integrated circuit according to claim 7, further comprising third power supply wiring that extends in said second direction in said wiring placement area and supplies a third power supply of higher voltage than said second power supply to said circuit blocks.

9. A semiconductor integrated circuit manufacturing method comprising:

a step of placing first power supply wiring that supplies a first power supply and second power supply wiring that supplies a second power supply of higher voltage than said first power supply;

a step of placing a plurality of circuit blocks;

a step of connecting said plurality of circuit blocks to first power supply wiring;

a step of extracting a circuit block that includes a critical path among said plurality of circuit blocks; and

a step of replacing connection of said circuit block that includes a critical path to first power supply wiring with connection of said circuit block that includes a critical path to second power supply wiring.

10. The semiconductor integrated circuit manufacturing method according to claim 9, further comprising a step of, after said step of replacement with connection of said circuit block that includes a critical path to second power supply wiring, performing said step of extracting said critical path, and making a voltage value of said second power supply higher than a previous voltage value until said critical path no longer exists.

11. The semiconductor integrated circuit manufacturing method according to claim 9, wherein:

said step of placing a plurality of circuit blocks further comprises a step of placing a plurality of circuit blocks that have a first threshold value;

said step being a step of replacing a first threshold value of a circuit block that includes said critical path with a second threshold value lower than said first threshold value after said step of extracting a circuit block that includes said critical path.

15. The semiconductor integrated circuit manufacturing method according to claim 10, wherein:

said step of placing a plurality of circuit blocks further comprises a step of placing a plurality of circuit blocks that have a first threshold value;

said step being a step of replacing a first threshold value of a circuit block that includes said critical path with a second threshold value lower than said first threshold value after said step of extracting a circuit block that includes said critical path.