Semiconductor integrated device

• US 20060046408A1
• Filed: 03/30/2005
• Published: 03/02/2006
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohsawa, Takashi
• Granted Patent: US 7,244,991 B2
• Time in Patent Office: Days
• US Class Current: 438/309
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7322 having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
• CPC Class Codes: H01L 29/735 Lateral transistors
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

A semiconductor integrated apparatus, comprising: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p type of first well diffusion region formed along the embedded insulation film in the support substrate below the NMOSFET; an n type of second well diffusion region formed along the embedded insulation film in the support substrate below the PMOSFET; and a conduction type of third well diffusion region formed along the embedded insulation film in the support substrate below the FBC.

Claims

1. A semiconductor integrated apparatus, comprising:

an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film;

an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other;

a p type of first well diffusion region formed along the embedded insulation film in the support substrate below the NMOSFET;

an n type of second well diffusion region formed along the embedded insulation film in the support substrate below the PMOSFET; and

a conduction type of third well diffusion region formed along the embedded insulation film in the support substrate below the FBC.

2. The semiconductor intergrated apparatus according to claim 1, wherein the first and second well diffusion regions are set to prescribed potentials, respectively, in order to avoid inversion of the SOI at a side near to the embedded insulation film in a region sandwiched by a channel region of the NMOSFET, a channel region of the PMOSFET and the embedded insulation film.

3. The semiconductor integrated apparatus according to claim 1, further comprising:

a conduction type of fourth well diffusion region formed in contact with lower surfaces of the first and second well diffusion regions.

4. The semiconductor integrated apparatus according to claim 3, further comprising:

an n type of fifth well diffusion region which is formed adjacent to the first well diffusion region, and formed along the embedded insulation film in contact with the fourth well diffusion region.

5. The semiconductor integrated apparatus according to claim 1, further comprising:

a first contact which extends upward from the first well diffusion region by passing through the embedded insulation film;

a second contact which extends upward from the second well diffusion region by passing through the embedded insulation film; and

a third contact which extends upward from the third well diffusion region by passing through the embedded insulation film,

wherein prescribed voltages are applied to the first to third well diffusion regions via the first to third contacts, respectively.

6. The semiconductor integrated apparatus according to claim 1, wherein the first well diffusion region is set to a voltage equal to or less than a source voltage of the NMOSFET;

and

the second well diffusion region is set to a voltage equal to or more than a source voltage of the PMOSFET.

7. The semiconductor integrated apparatus according to claim 6, wherein a source of the NMOSFET is 0V;

and

the first well diffusion region and the support substrate are set to 0V.

8. The semiconductor integrated apparatus according to claim 6, wherein a source of the NMOSFET is 0V;

and

the first well diffusion region and the support substrate are set to a negative potential.

9. A semiconductor integrated apparatus, comprising:

an SOI (Silicon On Insulator) substrate which has a conduction type of support substrate and an embedded insulation film;

a first well diffusion region which contacts a lower surface of the embedded insulation film;

a first and a second diffusion regions having conduction types different from each other, which are formed in the first well diffusion region separate from each other, and which contacts and are formed below the embedded insulation film;

a third diffusion region, which contacts and is formed below the embedded insulation film;

a first contact which extends upward from the first diffusion region by passing through the embedded insulation film;

a second contact which extends upward from the second diffusion region by passing through the embedded insulation film;

a third contact which extends upward from the third diffusion region by passing through the embedded insulation film;

a base electrode connected to the first contact;

an emitter electrode connected to the second contact; and

a collector electrode connected to the third contact.

10. The semiconductor integrated apparatus according to claim 9, wherein the support substrate, the second diffusion region and the third diffusion region are the first conduction type;

and

the first well diffusion region and the first diffusion region are the second conduction type.

11. The semiconductor integrated apparatus according to claim 9, further comprising:

a reference voltage generating circuit which outputs a reference voltage, the reference voltage generating circuit including;

a first and a second transistors connected in series between first and second supply voltage terminals;

a third transistor, a first impedance element, a second impedance element and a fourth transistor connected in series between the first and second supply voltage terminals; and

a differential amplifier which supplies a signal in accordance with a potential difference between a voltage of a connection node between the first and second transistors and a voltage of a connection node between the first impedance element and the second impedance element, to gates of the first and third transistors,

the reference voltage generating circuit outputting the reference voltage from a connection node between the third transistor and the first impedance element,

each of the second transistor and the fourth transistor being a bipolar transistor which has a base and a collector short-circuited to each other and operates as a current source, and

each of the second transistor and the fourth transistor having the first well diffusion region, the first diffusion region, the second diffusion region, the third diffusion region, the first contact, the second contact and the third contact.

12. A semiconductor integrated apparatus, comprising:

an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film;

a first conduction type of first diffusion region which contacts and is formed below the embedded insulation film;

a second conduction type of second diffusion region which contacts a lower surface of the embedded insulation film, and is formed separately from the first diffusion region;

a first conduction type of third well diffusion region which contacts the lower surface of the embedded insulation film, and is formed deeper than the first and second diffusion regions;

a first conduction type of fourth well diffusion region which contacts the lower surface of the embedded insulation film, and is formed deeper than the first and the second diffusion regions;

a first conduction type of fifth well diffusion region formed in contact with the third and fourth well diffusion regions;

a second conductive type of sixth well diffusion region which covers the first and second diffusion regions, and is positioned in a region separate from the support substrate by the third, fourth and fifth well diffusion regions;

a first contact which extends upward from the first diffusion region by passing through the embedded insulation film;

a second contact which extends upward from the second diffusion region by passing through the embedded insulation film;

a third contact which extends upward from the third well diffusion region by passing through the embedded insulation film;

a fourth contact which extends upward from the fourth well diffusion region by passing through the embedded insulation film;

a cathode electrode connected to the first contact;

an anode electrode connected to the second contact; and

a power supply terminal connected to the third and fourth contacts.

13. The semiconductor integrated apparatus according to claim 12, wherein the first conduction type is n-type;

and

the second conduction type is p-type.

14. The semiconductor integrated apparatus according to claim 12, further comprising:

a reference voltage generating circuit which outputs a reference voltage, the reference voltage generating circuit including;

a first transistor and a first diode connected directly between first and second supply voltage terminals;

a second transistor, a first impedance element, a second impedance element and a second diode connected in series between the first and second supply voltage terminals; and

a differential amplifier which supplies a signal in accordance with a potential difference between a voltage of a connection node between the first transistor and the first diode and a voltage of a connection node between the first impedance element and the second impedance element, to gates of the first and second transistors,

the reference voltage generating circuit outputting the reference voltage from a connection node between the second transistor and the first impedance element,

each of the first and second diodes having a the first diffusion region, the second diffusion region, the third well diffusion region, the fourth diffusion region, the fifth well diffusion region, the sixth well diffusion region, the first contact, the second contact, the third contact and the fourth contact.