Deep power saving by disabling clock distribution without separate clock distribution for power management logic
First Claim
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1. An apparatus for disabling clock distribution while a processor is in power save mode, comprising:
- means for toggling the clock distribution to the processor;
means for toggling signals external to the processor to activate the processor from the power save mode; and
means for using combinational logic to monitor the signals external to the processor.
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Abstract
An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.
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Citations
19 Claims
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1. An apparatus for disabling clock distribution while a processor is in power save mode, comprising:
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means for toggling the clock distribution to the processor;
means for toggling signals external to the processor to activate the processor from the power save mode; and
means for using combinational logic to monitor the signals external to the processor. - View Dependent Claims (2)
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3. An apparatus for disabling clock distribution while a processor is in power save mode, comprising:
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at least one logic gate for receiving a plurality of enable signals; and
combinational logic that is at least configured to relay the output of the clock distribution based on the output of the at least one logic gate. - View Dependent Claims (4, 5, 6, 7)
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8. A method for disabling clock distribution while a processor is in power save mode, comprising:
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toggling the clock distribution to the processor;
toggling signals external to the processor to activate the processor from the power save mode; and
using combinational logic to monitor the signals external to the processor. - View Dependent Claims (9)
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10. A method for disabling clock distribution while a processor is in power save mode, comprising:
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generating a plurality of power mode signals; and
disrupting the clock distribution to the processor based on the plurality of power mode signals. - View Dependent Claims (11, 12, 13, 14)
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15. A computer program product for disabling clock distribution while a processor is in power save mode, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:
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computer code for generating a plurality of power mode signals; and
computer code for disrupting the clock distribution to the processor based on the plurality of power mode signals. - View Dependent Claims (16, 17, 18, 19)
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Specification