Deep power saving by disabling clock distribution without separate clock distribution for power management logic

• US 20060123261A1
• Filed: 12/02/2004
• Published: 06/08/2006
• Est. Priority Date: 12/02/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wang, Michael Fan, Weitzel, Stephen Douglas, Stasiak, Daniel Lawrence, Riley, Mack Wayne
• Granted Patent: US 7,284,138 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.

Claims

1. An apparatus for disabling clock distribution while a processor is in power save mode, comprising:

means for toggling the clock distribution to the processor;

means for toggling signals external to the processor to activate the processor from the power save mode; and

means for using combinational logic to monitor the signals external to the processor.

2. The apparatus of claim 1, wherein the combinational logic further comprises a multiplexer (mux).

3. An apparatus for disabling clock distribution while a processor is in power save mode, comprising:

at least one logic gate for receiving a plurality of enable signals; and

combinational logic that is at least configured to relay the output of the clock distribution based on the output of the at least one logic gate.

4. The apparatus of claim 3, wherein the clock distribution further comprises a Phased Locked Loop (PLLs) for generating a plurality of clocking signals.

5. The apparatus of claim 3, wherein the at least one logic gate further comprises an AND gate.

6. The apparatus of claim 5, wherein the plurality of enable signals further comprises:

a power save mode acknowledge (PSM_ACK) signal generated by an external device; and

a clock enable (CLK_EN) signal generated by the processor.

7. The apparatus of claim 3, wherein the combinational logic further comprises a mux.

8. A method for disabling clock distribution while a processor is in power save mode, comprising:

toggling the clock distribution to the processor;

toggling signals external to the processor to activate the processor from the power save mode; and

using combinational logic to monitor the signals external to the processor.

9. The method of claim 8, wherein the step of using combinational logic further comprises ANDing the signals external to the processor and a signal from the processor.

10. A method for disabling clock distribution while a processor is in power save mode, comprising:

generating a plurality of power mode signals; and

disrupting the clock distribution to the processor based on the plurality of power mode signals.

11. The method of claim 10, wherein the step of generating further comprises:

receiving a PSM_ACK signal form an external device; and

generating a CLK_EN signal by the processor.

12. The method of claim 10, wherein the method further comprises logically combining the plurality of power mode signals to generate a disrupt signal.

13. The method of claim 12, wherein the step of disrupting further comprises employing combinational logic to disrupt the clock distribution.

14. The method of claim 12, wherein the step of logically combining further comprises ANDing the plurality of power mode signals.

15. A computer program product for disabling clock distribution while a processor is in power save mode, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:

computer code for generating a plurality of power mode signals; and

computer code for disrupting the clock distribution to the processor based on the plurality of power mode signals.

16. The computer program product of claim 15, wherein the computer code for generating further comprises:

computer code for receiving a PSM_ACK signal form an external device; and

computer code for generating a CLK_EN signal by the processor.

17. The computer program product of claim 15, wherein the computer program product further comprises computer code for logically combining the plurality of power mode signals to generate a disrupt signal.

18. The computer program product of claim 17, wherein the computer code for disrupting further comprises employing combinational logic to disrupt the clock distribution.

19. The computer program product of claim 17, wherein the computer code for logically combining further comprises ANDing the plurality of power mode signals.