Semiconductor device, wiring substrate, and method for manufacturing wiring substrate

• US 20060151870A1
• Filed: 11/21/2003
• Published: 07/13/2006
• Est. Priority Date: 11/21/2002
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Nishiyama, Tomohiro, Tago, Masamoto
• Granted Patent: US 7,728,439 B2
• Time in Patent Office: Days
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer (5) is provided on one surface of a silicon base (3). An electrode as the uppermost layer of the wiring layer (5) is provided with an external bonding bump (7). A through-electrode (4) is formed in the base (3) for electrically connecting the wiring layer (5) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip (1) by an internal bonding bump (6). The thermal expansion coefficient of the silicon base (3) is equivalent to that of the semiconductor chip (1) and not more than that of the wiring layer (5).

Claims

1. A semiconductor apparatus in which a semiconductor chip is mounted on a wiring substrate with Flip-Chip,

wherein the wiring substrate comprising:

a base substrate;

a wiring layer having an insulating layer and a wiring formed on a wiring layer formation surface which is one surface of the base substrate;

an electrode formed on a chip mounting surface which is a backside of the wiring layer formation surface of the base substrate; and

a through-electrode formed on the base substrate electrically connecting the wiring layer formed on the wiring layer formation surface and the electrode formed on the chip mounting surface,

wherein a thermal expansion coefficient of the base substrate is equal to a thermal expansion coefficient of the semiconductor chip, or less than a thermal expansion coefficient of the wiring layer,

wherein the semiconductor chip is bonded to the chip mounting surface with face-down.

2. A semiconductor apparatus according to claim 1, wherein a material of the base substrate is any one of a silicon, a ceramic, and a photosensitive glass.

3. A semiconductor apparatus according to claim 1, wherein a reinforcing frame is stuck at least on a part of outer part of the chip mounting position of the chip mounting surface.

4. A semiconductor apparatus according to claim 3, wherein a thermal expansion coefficient of the reinforcing frame is equal to the thermal expansion coefficient of the semiconductor chip, or less than the thermal expansion coefficient of the wiring layer.

5. A semiconductor apparatus according to claim 1, wherein a thickness of the base substrate, at least a part of outer part of the semiconductor chip mounting position at the chip mounting surface, is thicker than the semiconductor chip mounting position at the chip mounting surface.

6. A semiconductor apparatus according to claim 1, wherein a functional element is formed on at least any one of the wiring layer formation surface and the wiring layer.

7. A semiconductor apparatus according to claim 1, wherein the thermal expansion coefficient of the semiconductor chip is smaller than a thermal expansion coefficient of the wiring layer.

8. A wiring substrate which mounts a semiconductor chip with Flip-Chip,

wherein the wiring substrate comprising:

a base substrate;

a wiring layer having an insulating layer and a wiring formed on a wiring layer formation surface which is one surface of the base substrate;

an electrode formed on a chip mounting surface which is a backside of the wiring layer formation surface of the base substrate; and

a through-electrode formed on the base substrate electrically connecting the wiring layer formed on the wiring layer formation surface and the electrode formed on the chip mounting surface,

wherein a thermal expansion coefficient of the base substrate is equal to a thermal expansion coefficient of the semiconductor chip, or less than a thermal expansion coefficient of the wiring layer,

9. A wiring substrate according to claim 8, wherein a material of the base substrate is any one of a silicon, a ceramic, and a photosensitive glass.

10. A wiring substrate according to claim 8, wherein a reinforcing frame is stuck at least on a part of outer part of the chip mounting position of the chip mounting surface.

11. A wiring substrate according to claim 10, wherein a thermal expansion coefficient of the reinforcing frame is equal to the thermal expansion coefficient of the semiconductor chip, or less than the thermal expansion coefficient of the wiring layer.

12. A wiring substrate according to claim 8, wherein a thickness of the base substrate, at least a part of outer part of the semiconductor chip mounting position at the chip mounting surface, is thicker than the semiconductor chip mounting position at the chip mounting surface.

13. A wiring substrate according to claim 8, wherein a functional element is formed on at least any one of the wiring layer formation surface and the wiring layer.

14. A wiring substrate according to claim 8, wherein the thermal expansion coefficient of the semiconductor chip is smaller than a thermal expansion coefficient of the wiring layer.

15. A method for manufacturing a wiring substrate which comprises a base substrate and a wiring layer having an insulating layer and a wiring formed on a wiring layer formation surface, which is one surface of the base substrate, and mounts a semiconductor chip with Flip-Chip, the method comprising steps of:

forming a half-through-hole from the wiring layer formation surface of the base substrate;

forming a first electrode on the wiring layer formation surface by burying the half-through-hole with an electrically conductive material;

forming the wiring layer on the wiring layer formation surface; and

forming a second electrode for mounting the semiconductor chip by exposing the half-through-hole through thinning the base substrate from a backside of the wiring layer formation surface.

16. A method for manufacturing a wiring substrate according to claim 15, further comprising a step of:

thinning the base substrate by maintaining a step between at least one part of outer part of a semiconductor chip mounting position and the other part of the semiconductor chip mounting position, by making a work amount smaller at least at the one part of outer part of the semiconductor chip mounting position than the other part of the semiconductor chip mounting position.

17. A method for manufacturing a wiring substrate according to claim 15, further comprising a step of:

forming a functional element at a process forming the wiring layer.

18. A method for manufacturing a wiring substrate which comprises a base substrate and a wiring layer formed on a wiring layer formation surface, which is one surface of the base substrate, and mounts a semiconductor chip with Flip-Chip, the method comprising steps of:

forming the wiring layer on the wiring layer formation surface of the base substrate;

forming a through-hole which penetrates only the base substrate from a backside of the wiring layer formation surface of the base substrate; and

forming an electrode for mounting the semiconductor chip at the backside of the wiring layer formation surface by burying the through-hole with an electrically conductive material.

19. A method for manufacturing a wiring substrate according to claim 18, further comprising a step of:

thinning the base substrate by maintaining a step between at least one part of outer part of a semiconductor chip mounting position and other part of the semiconductor chip mounting position, by making a work amount smaller at least at the one part of outer part of the semiconductor chip mounting position than the other part of the semiconductor chip mounting position.

20. A method for manufacturing a wiring substrate according to claim 18, further comprising a step of:

forming a functional element at a process forming the wiring layer.