Optimizing write/erase operations in memory devices

• US 20060155917A1
• Filed: 01/13/2005
• Published: 07/13/2006
• Est. Priority Date: 01/13/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Di Sena, Angelo, Intini, Agata
• Granted Patent: US 7,363,421 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A method controls write/erase operations in a memory device including memory blocks that are exposed to wear as a result of repeated erasures. The method includes: storing the erase counts of the memory blocks, creating a chain storing the erase counts of the memory blocks that are available for writing at a certain instant of time, and selecting for writing, out of the blocks in the memory device available for writing, the block having the lowest erase count in the chain.

Claims

1. A method of controlling write/erase operations in a memory device including memory blocks, said blocks being exposed to wear as a result of repeated erasures, the method comprising:

storing erase counts of said memory blocks, each erase count reflecting the number of erasures of an associated one of the memory blocks;

creating a chain storing the erase counts of said memory blocks that are available for writing at a certain instant of time; and

selecting for writing, out of the blocks of said memory device available for writing, the block having the lowest erase count in said chain.

2. The method of claim 1, including the steps of:

writing data in said block having the lowest erase count in said chain; and

updating said chain of erase counts.

3. The method of claim 1, including the steps of:

arranging said blocks in said memory device in orderly positions; and

storing said erase count of each block in a table, entering as an i-th entry in said table the number of erasures performed on a block in an i-th position in said memory device.

4. The method of claim 1, including the steps of associating said memory device with a RAM memory and creating said chain in a portion of said RAM memory.

5. The method of claim 1, wherein each block is partitioned into a main area and a spare area, the method including the step of storing said erase count of each block in a table located in the main area of one of said blocks.

6. The method of claim 5, including the steps of providing pages for storing table entries of said table, wherein said pages contain a flag in said spare area of the one of said blocks.

7. The method of claim 1, including the steps of storing said erase count of each block in a table and providing pages for storing table entries of said table, wherein said pages contain a flag indicating that the pages store said table entries.

8. The method of claim 7, including the steps of searching said table within said memory device during power-on operation by recognizing the pages storing said table entries based on said flag.

9. The method of claim 8, including the steps of searching said table within said memory device starting from the last block in said memory device.

10. The method of claim 1, including the steps of:

storing said erase count of each block in a table;

selecting a last non-defective memory block in said memory device; and

writing said table in said non-defective memory block when said memory device is formatted for the first time.

11. The method of claim 10, wherein for each subsequent formatting operation of said memory device said table is updated by incrementing the erase counts of the memory blocks that will be erased.

12. The method of claim 1, including the step of creating said chain storing the erase counts of said memory blocks by storing for each said block available for writing:

a block number;

an associated erase count; and

a pointer to a subsequent element in the chain.

13. The method of claim 12, wherein said chain is ordered in a FIFO (First In First Out) way.

14. The method of claim 12, including the step of reconstructing said chain at every device power-on.

15. The method of claim 12, including the step of creating said chain storing the erase counts of said memory blocks by performing, for each said block available for writing, the operations of:

reading an associated erase count;

creating a corresponding element for said chain including a block number and said erase count previously read; and

inserting the element thus created in said chain.

16. The method of claim 1, including the steps of:

associating with said memory device a RAM memory;

detecting when the erase count for a given block value reaches a maximum storable value;

loading said erase counts in said RAM memory;

dividing by two said erase counts stored in said RAM memory; and

re-writing said divided erase counts in said memory device.

17. The method of claim 1, including the step of selecting said memory device as a flash memory device.

18. A computer system, comprising:

a memory device including memory blocks that are exposed to wear as a result of repeated erasures;

storing means for storing erase counts of the memory blocks, each erase count reflecting the number of erasures of an associated one of the memory blocks;

means for creating a chain storing the erase counts of the memory blocks that are available for writing at a certain instant of time; and

means for selecting for writing, out of the blocks of the memory device available for writing, the block having the lowest erase count in the chain.

19. The system of claim 18, further comprising:

means for removing an element of the chain corresponding to the block having the lowest erase count in the chain after the block is selected for writing.

20. The system of claim 18 wherein the means for storing the erase counts store the erase count of each block in a table in a last non-defective memory block in the memory device.

21. The system of claim 18 wherein the means for creating the chain include means for storing, for each the block available for writing, a chain element that includes:

a block number of the block;

the erase count of the block; and

a pointer to a subsequent element in the chain.

22. The system of claim 18, wherein the chain is ordered in a FIFO (First In First Out) way.

23. The system of claim 18 wherein the means for creating include means for reconstructing the chain at every device power-on.

24. The system of claim 18, wherein the means for creating the chain include means for:

accessing each block of the memory device that is available for writing;

reading from the storing means the erase count associated with the block;

creating a corresponding element for the chain including a block number and the erase count previously read; and

inserting the element thus created in the chain.

25. The system of claim 18, further comprising:

a RAM memory;

means for detecting when the erase count for a given block value reaches a maximum storable value;

means for loading the erase counts in the RAM memory;

means for dividing by two the erase counts stored in the RAM memory; and

means for writing the divided erase counts in the memory device.

26. A computer product for controlling write/erase operations in a memory device including memory blocks that are exposed to wear as a result of repeated erasures, the computer product being loadable into a memory of a digital computer and comprising instruction code portions for performing, when the product is run on a computer, the following operations:

storing erase counts of the memory blocks, each erase count reflecting the number of erasures of an associated one of the memory blocks;

creating a chain storing the erase counts of the memory blocks that are available for writing at a certain instant of time; and

selecting for writing, out of the blocks of the memory device available for writing, the block having the lowest erase count in the chain.

27. The computer product of claim 26, further including instruction code portions for performing, when the product is run on a computer, the following operations:

writing data in the block having the lowest erase count in the chain; and

updating the chain of erase counts.

28. The computer product of claim 26, further including instruction code portions for performing, when the product is run on a computer, the following operations:

storing the erase count of each block in a table in a selected block of the memory device;

storing in the selected block a flag indicating that the table is stored in the selected block.

29. The computer product of claim 26, further including instruction code portions for performing, when the product is run on a computer, the following operation:

creating the chain storing the erase counts of the memory blocks by storing, for each the block available for writing;

a block number, an associated erase count, and a pointer to a subsequent element in the chain.

30. The computer product of claim 26, further including instruction code portions for performing, when the product is run on a computer, the following operations:

creating the chain storing the erase counts of the memory blocks by performing, for each the block available for writing, the operations of;

reading an associated erase count;

creating a corresponding element for the chain including a block number and the erase count previously read; and

inserting the element thus created in the chain.

31. The computer product of claim 26, further including instruction code portions for performing, when the product is run on a computer, the following operations:

associating with the memory device a RAM memory;

detecting when the erase count for a given block value reaches a maximum storable value;

loading the erase counts in the RAM memory;

dividing by two the erase counts stored in the RAM memory; and

re-writing the divided erase counts in the memory device.