Image processor circuits, systems, and methods
1 Assignment
0 Petitions
Accused Products
Abstract
An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.
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Citations
38 Claims
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1-7. -7. (canceled)
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8. A correlated double sampler and variable gain amplifier (CDSVGA) circuit for receiving CCD data, comprising:
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a first fixed capacitor for receiving CCD data;
a first amplifier connected to said first fixed capacitor for amplifying CCD data, said first amplifier connected to said first fixed capacitor;
a first variable capacitor connected in parallel with said first amplifier;
a first switch connected in parallel with said first variable capacitor, said first switch being clocked at a first clock phase;
a second variable capacitor connected to said first amplifier;
a second amplifier connected to said second variable amplifier;
a second fixed capacitor connected in parallel with said second amplifier; and
a second switch connected in parallel with said second fixed amplifier;
said second switch being clocked at a second clock phase. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38)
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9-29. -29. (canceled)
Specification