Image processor circuits, systems, and methods

• US 20060197847A1
• Filed: 05/01/2006
• Published: 09/07/2006
• Est. Priority Date: 05/08/1998
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Hansford, Alan Wayne, Wang, Caiyi, Welland, David R., Holberg, Douglas R., Azim, Syed Khalid, Chao, Shih-Chung, Harris, Brannon Craig, Itani, Nadi Rafik, Johnson, Sandra Marie, Prabala, Ash
• Granted Patent: US 7,289,145 B2
• Time in Patent Office: Days
• US Class Current: 348/229.1
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

Claims

1-7. -7. (canceled)

8. A correlated double sampler and variable gain amplifier (CDSVGA) circuit for receiving CCD data, comprising:

a first fixed capacitor for receiving CCD data;

a first amplifier connected to said first fixed capacitor for amplifying CCD data, said first amplifier connected to said first fixed capacitor;

a first variable capacitor connected in parallel with said first amplifier;

a first switch connected in parallel with said first variable capacitor, said first switch being clocked at a first clock phase;

a second variable capacitor connected to said first amplifier;

a second amplifier connected to said second variable amplifier;

a second fixed capacitor connected in parallel with said second amplifier; and

a second switch connected in parallel with said second fixed amplifier;

said second switch being clocked at a second clock phase.

30. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, wherein the first switch alternates between open and closed states in accordance with the first clock phase.

31. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, wherein the second switch alternates between open and closed states in accordance with the second clock phase.

32. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, wherein a total gain of the CDSVGA circuit is adjustable by varying values for the first variable capacitor and the second variable capacitor.

33. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, wherein a total gain of the CDSVGA circuit is a product of a divided value derived from a value of the first fixed capacitor divided by a value of the second fixed capacitor and another divided value derived from a value of the second variable capacitor divided by a value of the first variable capacitor.

34. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, further comprises a two phase non-overlapping clock for performing the correlated double sampling operations.

35. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, wherein the two phase non-overlapping clock allows video signals to be passed to an output while maintaining a positive polarity signal.

36. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, wherein the first fixed capacitor, the first amplifier, the first variable capacitor, and the first switch perform correlated double sampling by sampling a feed-through level across the first fixed capacitor when the first clock phase is high and an amplifier output of the first amplifier follows an input gain in accordance with a divided capacitor value that is derived from a negative of a value of the first fixed capacitor divided by a value of the first variable capacitor when the first clock phase is low.

37. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 8, wherein the second fixed capacitor, the second amplifier, the second variable capacitor, and the second switch perform correlated double sampling by sampling a feed-through level across the second fixed capacitor when the second clock phase is high and an amplifier output of the second amplifier follows an input gain in accordance with a divided capacitor value that is derived from a negative of a value of the second fixed capacitor divided by a value of the second variable capacitor when the second clock phase is low.

38. The correlated double sampler and variable gain amplifier (CDSVGA) circuit according to claim 37, further comprises a two phase non-overlapping clock for performing the correlated double sampling operations and the second clock phase is controlled by a second phase of the two phase non-overlapping clock, which adds a half clock delay that is effective to maintain a positive output voltage with respect to a reference voltage.

9-29. -29. (canceled)