Plasma Treatment at Film Layer to Reduce Sheet Resistance and to Improve Via Contact Resistance
First Claim
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1. A semiconductor device, comprising:
- a substrate;
a plurality of logic devices located over the substrate;
an insulating layer located over the logic devices and including a plurality of recesses exposing underlying ones of the logic devices;
an agglutinating layer located over the insulating layer including within the plurality of recesses, the agglutinating layer having an enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen;
a barrier layer located over the plasma-treated agglutinating layer including within the plurality of recesses; and
a conductive layer located over the barrier layer including within the plurality of recesses.
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Abstract
A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a substrate;
a plurality of logic devices located over the substrate;
an insulating layer located over the logic devices and including a plurality of recesses exposing underlying ones of the logic devices;
an agglutinating layer located over the insulating layer including within the plurality of recesses, the agglutinating layer having an enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen;
a barrier layer located over the plasma-treated agglutinating layer including within the plurality of recesses; and
a conductive layer located over the barrier layer including within the plurality of recesses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device, comprising:
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a logic device located over a substrate;
an insulating layer located over the logic device, wherein a recess in the insulating layer exposes at least a portion of the logic device;
an agglutinating layer located over the insulating layer and within the recess, the agglutinating layer having an enlarged grain size due to plasma treatment;
a barrier layer located over the plasma-treated agglutinating layer and within the recess; and
a conductive layer located over the barrier layer and within the recess. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification