Plasma Treatment at Film Layer to Reduce Sheet Resistance and to Improve Via Contact Resistance

• US 20060216916A1
• Filed: 05/22/2006
• Published: 09/28/2006
• Est. Priority Date: 05/10/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Zhang, Wei, Chou, Yu-Hua, Tseng, Chi-Chan, Luo, Tzo-Hung, Yang, Jong-Chen, Tsai, Jian-Shin
• Granted Patent: US 7,358,612 B2
• Time in Patent Office: Days
• US Class Current: 438/586
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation

Abstract

A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of logic devices located over the substrate;

an insulating layer located over the logic devices and including a plurality of recesses exposing underlying ones of the logic devices;

an agglutinating layer located over the insulating layer including within the plurality of recesses, the agglutinating layer having an enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen;

a barrier layer located over the plasma-treated agglutinating layer including within the plurality of recesses; and

a conductive layer located over the barrier layer including within the plurality of recesses.

2. The semiconductor device recited in claim 1 wherein the grain size of the plasma-treated agglutinating layer is about 20% larger than prior to plasma treatment.

3. The semiconductor device recited in claim 1 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a sheet resistance ranging between about 70 Ω

/nm² and about 130 Ω

/nm².

4. The semiconductor device recited in claim 1 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a contact resistance ranging between about 6 Ω

/nm² and about 9 Ω

/nm².

5. The semiconductor device recited in claim 4 wherein the contact has a sheet resistance ranging between about 70 Ω

/nm² and about 130 Ω

/nm².

6. The semiconductor device recited in claim 1 wherein the agglutinating layer comprises a material selected from the group consisting of:

Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.

7. The semiconductor device recited in claim 1 wherein the agglutinating layer has a thickness ranging between about 100 angstroms and about 160 angstroms.

8. The semiconductor device recited in claim 1 wherein the barrier layer comprises a material selected from the group consisting of:

Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.

9. The semiconductor device recited in claim 1 wherein the barrier layer includes a plurality of plasma densified TiN layers.

10. A semiconductor device, comprising:

a logic device located over a substrate;

an insulating layer located over the logic device, wherein a recess in the insulating layer exposes at least a portion of the logic device;

an agglutinating layer located over the insulating layer and within the recess, the agglutinating layer having an enlarged grain size due to plasma treatment;

a barrier layer located over the plasma-treated agglutinating layer and within the recess; and

a conductive layer located over the barrier layer and within the recess.

11. The semiconductor device recited in claim 10 wherein the agglutinating layer has the enlarged grain size due to plasma treatment with a process chemistry comprising nitrogen and hydrogen.

12. The semiconductor device recited in claim 10 wherein the grain size of the plasma-treated agglutinating layer is about 20% larger than prior to plasma treatment.

13. The semiconductor device recited in claim 10 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a sheet resistance ranging between about 70 Ω

/nm² and about 130 Ω

/nm².

14. The semiconductor device recited in claim 10 wherein the plasma-treated agglutinating layer, the barrier layer and the conductive layer collectively form a contact having a contact resistance ranging between about 6 Ω

/nm² and about 9 Ω

/nm².

15. The semiconductor device recited in claim 14 wherein the contact has a sheet resistance ranging between about 70 Ω

/nm² and about 130 Ω

/nm².

16. The semiconductor device recited in claim 10 wherein the agglutinating layer comprises a material selected from the group consisting of:

Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.

17. The semiconductor device recited in claim 10 wherein the agglutinating layer has a thickness ranging between about 100 angstroms and about 160 angstroms.

18. The semiconductor device recited in claim 10 wherein the barrier layer comprises a material selected from the group consisting of:

Ti, Ta, TiW, TiN, TaN, SiOC, and SiC.

19. The semiconductor device recited in claim 10 wherein the barrier layer includes a plasma-densified layer.

20. The semiconductor device recited in claim 10 wherein the barrier layer includes a plurality of plasma-densified TiN layers.