Robust index storage for non-volatile memory
First Claim
1. A method of operating a non-volatile memory device, comprising:
- looking up a logical sector address of a memory access to the non-volatile memory in a hierarchal address translation data structure to translate the logical sector address to a physical sector address, wherein the hierarchal address translation data structure contains two or more Tables/data structures arranged in a hierarchal data tree; and
accessing the physical sector address in the non-volatile memory device.
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Abstract
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.
141 Citations
74 Claims
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1. A method of operating a non-volatile memory device, comprising:
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looking up a logical sector address of a memory access to the non-volatile memory in a hierarchal address translation data structure to translate the logical sector address to a physical sector address, wherein the hierarchal address translation data structure contains two or more Tables/data structures arranged in a hierarchal data tree; and
accessing the physical sector address in the non-volatile memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of translating a logical address to a physical address in a memory device, comprising:
looking up a logical address in a hierarchal address translation data structure to translate the logical address to a physical address, wherein the hierarchal address translation data structure contains two or more Tables/data structures arranged in a hierarchal data tree. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of updating a hierarchal address translation data structure containing two or more Tables/data structures arranged in a hierarchal data tree and storing address translation data used to translate a logical address to a physical address, comprising:
traversing up the hierarchal address translation data structure, starting with a Table storing a changed address translation entry, the traversing further comprising;
checking if update space remains in a changed data entry or address pointer data entry in a current Table/data structure of a current level of the hierarchal address translation data structure;
updating the changed data entry or address pointer data entry when update space is available, and ending the update of the hierarchal address translation data structure;
creating a new Table/data structure when the changed data entry cannot be updated in the current Table/data structure;
copying the most-current entries/pointers to the new Table/data structure;
ending the update of the hierarchal address translation data structure if the current Table/data structure is at a top level of the hierarchal address translation data structure;
traversing up to a next level of the hierarchal address translation data structure when the current Table/data structure is not at the top level of the hierarchal address translation data structure; and
repeating updating on a parent Table/data structure of the next level to change an address pointer in the parent Table/data structure from the current to the new Table/data structure. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
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33. A method of abstracting logical addresses to physical addresses of a memory device utilizing an address translation layer, comprising:
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looking up a logical address with an address translation table and translating the logical address to a logical erase block ID; and
translating the logical erase block ID to a physical erase block ID utilizing a Logical to Physical Erase Block Translation Table. - View Dependent Claims (34, 35, 36, 37)
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38. A method of storing address translation data in a non-volatile memory array, comprising:
storing address translation data in a hierarchal address translation data structure of two or more Tables/data structures, where the two or more Tables/data structures are arranged in a hierarchal tree. - View Dependent Claims (39, 40, 41, 42)
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43. A method of initiating operation of a non-volatile memory device, comprising:
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searching a defined area of the non-volatile memory device to locate an Entry Point data structure; and
loading configuration information for the non-volatile memory device from the Entry Point data structure. - View Dependent Claims (44, 45, 46)
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47. A non-volatile memory device, comprising:
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a non-volatile memory array having a plurality of non-volatile memory cells; and
a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the non-volatile memory array. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. A Flash memory device, comprising:
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a memory array having a plurality of non-volatile memory cells arranged in a plurality of erase blocks, each erase block containing a plurality of clusters of one or more consecutively addressed sectors; and
a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the one or more erase blocks of the plurality of erase blocks. - View Dependent Claims (60, 61, 62, 63, 64, 65)
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66. A system, comprising:
a host coupled to a non-volatile memory device, wherein the system is adapted to translate logical addresses to physical addresses in the non-volatile memory device utilizing hierarchal address translation data. - View Dependent Claims (67, 68, 69, 70, 71, 72, 73, 74)
Specification