Seamless stitching of patterns formed by interference lithography

• US 20070023692A1
• Filed: 06/17/2006
• Published: 02/01/2007
• Est. Priority Date: 06/17/2005
• Status: Active Grant

• Current Assignee: Vincent E. Stenger
• Original Assignee: Vincent E. Stenger
• Inventors: Stenger, Vincent
• Granted Patent: US 7,718,326 B2
• Time in Patent Office: Days
• US Class Current: 250/492.200
• CPC Class Codes: G03F 7/70408 Interferometric lithography; Holographic lithography; Self-imaging lithography, e.g. utilizing the Talbot effect
• CPC Class Codes: G03F 7/70475 Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
• CPC Class Codes: G03F 9/7011 Pre-exposure scan; original with original holder alignment; Prealignment, i.e. workpiece with workpiece holder
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection

Abstract

This invention addresses the scalability problem of periodic “nanostructured” surface treatments such as those formed by interference lithography. A novel but simple method is described that achieves seamless stitching of nanostructure surface textures at the pattern exposure level. The described tiling approach will enable scaling up of coherent nanostructured surfaces to arbitrary area sizes. Such a large form factor nanotechnology will be essential for fabricating large aperture, coherent diffractive elements. Other applications include high performance, antiglare/antireflection and smudge resistant Motheye treatments for display products such as PDA'"'"'s, laptop computers, large screen TV'"'"'s, cockpit canopies, instrument panels, missile and targeting domes, and, more recently, “negative-index” surfaces. Although ideal for seamless stitching of nanometer scale patterns, the technology is broadly applicable to any situation where an arbitrarily large area needs to be seamlessly tiled with a smaller base pattern that has periodic overlap able boundaries.

Claims

1. A method of tile and stitch alignment as described by FIG. 4 and associated text, including:

partially overlapping exposure patterns;

post exposure impressions are used as relative position references for subsequent stitched exposures;

comparison of pre exposure patterns with post exposure impressions within the overlap regions to determine degree of mesh or stitch alignment between pattern exposure steps; and

each new tiled pattern can be stitched seamlessly with previous exposed patterns.

2. A method of generating pre and post exposure pattern stitch alignment error signals, including:

the self-masking method for monitoring stitch alignment error magnitude as described in FIG. 5 and associated text including;

a suitable contrast photosensitive material layer or layers with sufficient bleaching properties to enable creation of a pattern transmission mask after each full exposure suitable for stitch alignment; and

a suitably transparent or reflective substrate.

the self-masking method for monitoring stitch alignment error magnitude for low contrast photoresists as described in FIG. 7, including;

a contrast enhancement material layer or layers with sufficient bleaching properties to enable creation of a pattern transmission mask after each full exposure suitable for stitch alignment; and

a suitably transparent or reflecting substrate

the method of comparing pre and post exposure pattern stitch alignment error polarity by imaging of the transmitted or reflected pattern signal intensity in the stitch overlap regions as presented by FIG. 14, and associated text including;

a transmitted or reflected alignment signal image focusing and capture device; and

an image processing device for converting the image to a suitable stitch alignment servo signal.

3. The Interference lithography automatic pattern stitching apparatus of FIG. 10, including:

A plurality of interfering exposure beams with attenuation and differential phase controls;

coarse positioner or positioners and control for rough stitch tile positioning;

a fine positioning stage with resolution suitable to the stitched pattern feature periods;

sweep and bias generation and controls for dithering and setting stitch alignment fine positions along all stitch axes;

sensor apparatus to collect transmitted light alignment signal intensities and images during pre and post exposure steps as presented by FIG. 11, FIG. 12, FIG. 13 and associated text;

a lock-in amplifer or other device for reducing the effects of electronic and ambient radiation noise; and

a state machine, such as a computer, for alignment feedback signal processing and automatic tiling and stitch alignment control using an algorithm based on the flow diagram of FIG. 8