Data processing method and device

• US 20070050603A1
• Filed: 07/24/2003
• Published: 03/01/2007
• Est. Priority Date: 08/07/2002
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, May, Frank, Weinhardt, Markus, Baumgarte, Volker, Becker, Jurgen
• Granted Patent: US 8,156,284 B2
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3455 using stride
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Claims

1-7. -7. (canceled)

8. A method of simultaneously operating a sequential processor and a reconfigurable array, comprising:

transferring data from a data cache into a reconfigurable array; and

writing results produced from the data and in the reconfigurable array to a destination.

9. The method according to claim 8, wherein said destination is upstream of an arithmetic logic unit of the sequential processor.

10. The method according to claim 9, wherein data output from the reconfigurable array is, at least in part, fed into a data path of the sequential processor downstream of decoding circuitry of the sequential processor.

11. The method according to claim 9, wherein the arithmetic logic unit of the sequential processor is adapted to perform at least one operation on data output from the reconfigurable array.

12. The method according to claim 11, wherein at least one of:

the arithmetic logic unit includes circuitry for at least one of multiplication and division; and

the at least one operation includes at least one of multiplication, division, and norming.

13. The method according to claim 8, wherein data output from the reconfigurable array is selectably writable to a memory location other than any of the cache and a register of the sequential processor.

14. The method according to claim 8, wherein the destination is at least one of downstream of an arithmetic logic unit and upstream of the cache.

15. The method according to claim 14, wherein the cache is coupled to the sequential processor.