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Memory systems with column read to an arithmetic operation circuit, pattern detector circuits and methods and computer program products for the same

  • US 20070080856A1
  • Filed: 10/11/2005
  • Published: 04/12/2007
  • Est. Priority Date: 10/11/2005
  • Status: Active Grant
First Claim
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1. A memory system, comprising:

  • an array of storage cells arranged in a row and column arrangement;

    a plurality of data write lines coupled to the array and configured to supply data into a selected row of the array;

    a plurality of data read lines coupled to the array and configured to receive data from a selected column of the array in a single read operation; and

    an arithmetic operation circuit coupled to the plurality of data read lines that is configured to generate a result value based on data read from the storage cells of a selected column of the array.

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