Memory systems with column read to an arithmetic operation circuit, pattern detector circuits and methods and computer program products for the same

• US 20070080856A1
• Filed: 10/11/2005
• Published: 04/12/2007
• Est. Priority Date: 10/11/2005
• Status: Active Grant

• Current Assignee: Sony Ericsson Mobile Communications AB (Sony Group Corp.)
• Original Assignee: Sony Ericsson Mobile Communications AB (Sony Group Corp.)
• Inventors: Camp, William
• Granted Patent: US 7,477,186 B2
• Time in Patent Office: Days
• US Class Current: 342/357.770
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Memory systems include an array of storage cells arranged in a row and column arrangement. A plurality of data write lines coupled to the array are configured to supply data into a selected row of the array. A plurality of data read lines coupled to the array are configured to receive data from a selected column of the array in a single read operation. An arithmetic operation circuit coupled to the plurality of data read lines is configured to generate a result value based on data read from the storage cells of a selected column of the array. Methods of detecting a pattern, such as a color code pattern, are also provided.

Claims

1. A memory system, comprising:

an array of storage cells arranged in a row and column arrangement;

a plurality of data write lines coupled to the array and configured to supply data into a selected row of the array;

a plurality of data read lines coupled to the array and configured to receive data from a selected column of the array in a single read operation; and

an arithmetic operation circuit coupled to the plurality of data read lines that is configured to generate a result value based on data read from the storage cells of a selected column of the array.

2. The memory system of claim 1, further comprising a control circuit configured to select the storage cells in a selected row of the array responsive to a write address input signal by coupling the data write lines to the storage cells in the selected row and to select the storage cells in a selected column of the array responsive to a read address input signal by coupling the data read lines to the storage cells in the selected column to provide data from the storage cells in the selected column to the arithmetic operation circuit.

3. The memory system of claim 2, wherein the write lines are substantially orthogonal to the read lines.

4. The memory system of claim 3, further comprising a second plurality of data read lines coupled to the array and configured to receive data from a selected row of the array in a single read operation.

5. The memory system of claim 2, wherein the arithmetic operation circuit comprises a pattern detector configured to detect a pattern based on a comparison of the data read from the storage cells of the selected column of the array to a candidate pattern and to provide a pattern detect signal as the result value.

6. The memory system of claim 5, wherein the pattern detector is configured to detect a color code pattern from a Global Positioning System (GPS) satellite and wherein the pattern detect signal comprises an identification of the GPS satellite when the comparison indicates that data read corresponds to a candidate pattern associated with the GPS satellite.

7. The memory system of claim 6, wherein the control circuit is configured to write data corresponding to acquired data from a plurality of sequential chips of the color code pattern from a first sample of a received signal in a first row of the array and from subsequent samples in subsequent rows of the array to provide a plurality of data associated with respective ones of the sequential chips in corresponding columns of the array and wherein the pattern detector is configured to determine an energy associated with the sequential chips based on data read from a plurality of selected columns of the array to determine if the data read from the array corresponds to the candidate pattern associated with the GPS satellite.

8. A GPS circuit including the memory system of claim 7, further comprising:

a receiver configured to receive a location detection signal from the GPS satellite to provide a received signal; and

a controller configured to repeatedly sample the received signal at a candidate start time and at a chip rate of the candidate pattern associated with the GPS satellite to generate a plurality of sets of data samples and to store the plurality of sets of data samples in the storage cells of selected rows of the array, wherein each of the data sets is stored in an associated row of the array selected by the controller in a single read operation.

9. The GPS circuit of claim 8, wherein the controller is further configured to determine a pseudo-range to the GPS satellite based on the received signal and the identification of the GPS satellite.

10. The GPS circuit of claim 9, wherein the array of storage cells includes a number of rows corresponding to a coherent integration period of the GPS circuit and a number of columns corresponding to a number of data samples in a set of data samples.

11. The memory system of claim 7 wherein the pattern detector is configured to compare the data read from the array to a plurality of candidate patterns associated with different GPS satellites.

12. The memory system of claim 2, wherein the arithmetic operation circuit comprises a summer configured to sum the data read from the storage cells of the selected column of the array and to provide the sum as the result value.

13. The memory system of claim 12, wherein the arithmetic operation circuit further comprises a comparator configured to compare the sum result value to a reference value and to provide a result of the comparison as the result value.

14. The memory system of claim 13, wherein the arithmetic operation circuit is configured to store the sum result value and/or the comparison result value.

15. A mobile device including the memory system of claim 4 and a GPS receiver coupled thereto.

16. The mobile device of claim 15, further comprising a transceiver configured to communicate with a wide area cellular communications network.

17. A method for detecting a pattern, the method comprising:

obtaining a plurality of sequenced data values;

storing the sequenced data values in a selected row of an array of storage cells arranged in a row and column arrangement;

selecting a different row of the array; and

repeating obtaining a plurality of sequenced data values, storing the sequenced data values and selecting a different row a plurality of times; and

then

reading the stored data values from a selected column of the array of storage cells into a pattern detector in a single read operation; and

detecting the pattern based on the read stored data values.

18. The method of claim 17, wherein obtaining a plurality of sequenced data values includes sampling a signal to obtain the plurality of sequenced data values, the plurality of sequenced data values being representative of the signal, and wherein detecting the pattern comprises detecting the pattern in the sampled signal.

19. The method of claim 17, wherein obtaining a plurality of sequenced data values includes storing the data values in a first memory and wherein storing the sequenced data values in a selected row includes reading the sequenced data values from the first memory and wherein repeating obtaining a plurality of sequenced data values includes selecting a different plurality of the stored data values in the first memory.

20. The method of claim 19, wherein reading the stored data values further comprises reading the stored data values from a plurality of the columns of the array of storage cells into the pattern detector, wherein each of the plurality of columns of the array of storage cells is read into the pattern detector in a single read operation.

21. The method of claim 20, wherein reading the stored data values and detecting the pattern comprise:

reading the stored data values into a summer of the pattern detector;

summing the read data values;

selecting a different column of the array; and

repeating reading the stored data values, summing the read data values and selecting a different column a plurality of times to generate a plurality of sums of read data values from respective columns of the array of storage cells; and

detecting the pattern in the sampled signal based on the plurality of sums.

22. The method of claim 21, wherein detecting the pattern in the sampled signal based on the plurality of sums includes comparing the respective sums to a reference value.

23. The method of claim 17, wherein detecting the pattern comprises detecting a Primary Synchronization Channel (SCH) in a code division multiple access (CDMA) downlink signal and/or detecting a Secondary SCH in the CDMA downlink signal.

24. The method of claim 17, wherein detecting the pattern comprises determining a location of a predetermined bit sequence comprising a subset of bits within a Primary Synchronization Channel (SCH) bit sequence in a code division multiple access (CDMA) downlink signal, the sequenced data values stored in each row corresponding to respective repeats of the Primary SCH and wherein determining the location of the predetermined bit sequence is followed by:

storing respective repeats of the predetermined bit sequence into respective rows of the array of storage cells;

reading the stored respective repeats of the predetermined bit sequence from a selected column of the array of storage cells into the pattern detector in a single read operation; and

identifying the predetermined bit sequence as corresponding to one of a plurality of candidate bit sequences based on the read stored respective repeats of the predetermined bit sequence.

25. A computer program product for detecting a pattern, the computer program product comprising computer program code embodied in a computer readable medium, the computer program code comprising program code configured to carry out the method of claim 21.

26. A computer program product for detecting a pattern, the computer program product comprising computer program code embodied in a computer readable medium, the computer program code comprising program code configured to carry out the method of claim 17.

27. A method for detecting a Global Positioning System (GPS) color code pattern, the method comprising:

receiving a location detection signal from a GPS satellite to provide a received signal;

sampling the received signal at a candidate start time and at a chip rate of a candidate color code pattern associated with the GPS satellite to generate a set of time sequenced data samples;

storing the set of data samples in a selected row of an array of storage cells arranged in a row and column arrangement;

selecting a next candidate start time and a different row of the array; and

repeating receiving a location detection signal, sampling the received signal, storing the sequenced data samples and selecting a next candidate start time and a different row a plurality of times; and

then

repeatedly reading the stored data samples from respective selected columns of the array of storage cells into a pattern detector in a single read operation per column; and

detecting the color code pattern based on the read stored data samples and the candidate color code pattern associated with the GPS satellite.

28. The method of claim 27 wherein detecting the color code pattern includes:

summing the data samples from each column read into the pattern detector to determine energy levels associated with respective ones of the columns that correspond to respective time sequence positions in the received signal;

comparing the respective energy levels to a reference value to generate corresponding comparison result values corresponding to the respective time sequence positions in the received signal;

comparing the comparison result values to values in the candidate color code pattern associated with a same time sequence position.

29. The method of claim 28 wherein comparing the comparison results includes comparing the comparison results to a plurality of candidate color code patterns to determine an identification of the GPS satellite providing the received location detection signal and wherein the method further comprises determining a pseudo-range to the GPS satellite based on the received location signal and determining a position of the GPS satellite based on the identification of the GPS satellite.

30. The method of claim 29 wherein selecting a next candidate start time comprises selecting a same candidate start time a plurality of times.

31. The method of claim 29 wherein a same reference level is used for a plurality of the energy levels.