Semiconductor devices and methods of manufacturing the same
First Claim
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1. A method of manufacturing a semiconductor device, comprising:
- forming an NMOS transistor on a substrate;
forming a first interlayer dielectric layer on the NMOS transistor; and
dehydrogenating the first interlayer dielectric layer.
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Abstract
Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
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Citations
54 Claims
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1. A method of manufacturing a semiconductor device, comprising:
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forming an NMOS transistor on a substrate;
forming a first interlayer dielectric layer on the NMOS transistor; and
dehydrogenating the first interlayer dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of manufacturing a semiconductor device, comprising:
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forming an NMOS transistor on a substrate;
forming a first interlayer dielectric layer, which includes an O3-TEOS layer having a tensile stress, on the NMOS transistor; and
dehydrogenating the first interlayer dielectric layer. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A semiconductor device, comprising:
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an NMOS transistor comprising a gate dielectric layer and a gate electrode on a substrate;
a liner layer on the NMOS transistor, the liner layer having a tensile stress; and
a dehydrogenated first interlayer dielectric layer on the liner layer, the dehydrogenated first interlayer dielectric layer having a tensile stress that is increased due to dehydrogenation thereof;
wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer and the dehydrogenated first interlayer dielectric layer is represented by t2, and wherein t2/t1≧
1.14. - View Dependent Claims (38, 39, 40, 41, 42, 43)
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44. A semiconductor device, comprising:
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an NMOS transistor on a substrate;
a first interlayer dielectric layer on the NMOS transistor, the first interlayer dielectric layer having a tensile stress due to dehydrogenation of the first interlayer dielectric layer; and
a second interlayer dielectric layer on the first interlayer dielectric layer, the second interlayer dielectric layer having a stress smaller than that of the first interlayer dielectric layer. - View Dependent Claims (45, 46, 47, 48, 49, 50)
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51. A semiconductor device, comprising:
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an NMOS transistor and a PMOS transistor on a semiconductor substrate; and
a first interlayer dielectric layer on the NMOS and PMOS transistors, wherein the first interlayer dielectric layer comprises nitrogen and/or germanium ions implanted into a portion of the first interlayer dielectric layer on the PMOS transistor. - View Dependent Claims (52, 53, 54)
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Specification