Semiconductor devices and methods of manufacturing the same

• US 20070105297A1
• Filed: 11/07/2006
• Published: 05/10/2007
• Est. Priority Date: 11/07/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Dong-suk, Jeong, Yong-kuk, Kim, Andrew-tae
• Granted Patent: US 7,867,867 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming an NMOS transistor on a substrate;

forming a first interlayer dielectric layer on the NMOS transistor; and

dehydrogenating the first interlayer dielectric layer.

2. The method of claim 1, wherein dehydrogenating the first interlayer dielectric layer changes a stress of the first interlayer dielectric layer.

3. The method of claim 1, wherein dehydrogenating the first interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere.

4. The method claim 3, wherein the dehydrogenation gas comprises N₂, O₂, O₃, N₂O, H₂, and/or D₂ a combination thereof.

5. The method of claim 1, wherein the first interlayer dielectric layer has a tensile stress of at least about 200 MPa after dehydrogenization.

6. The method of claim 1, wherein the first interlayer dielectric layer comprises O₃-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, and/or TOSZ.

7. The method of claim 1, further comprising forming contacts connected to the NMOS transistor in the first interlayer dielectric layer after forming the first interlayer dielectric layer.

8. The method of claim 1, further comprising forming a second interlayer dielectric layer on the first interlayer dielectric layer after dehydrogenating the first interlayer dielectric layer, wherein the second interlayer dielectric layer has a stress smaller than a stress of the first interlayer dielectric layer after dehydrogenating the first interlayer dielectric layer.

9. The method of claim 1, further comprising forming a capping layer on the first interlayer dielectric layer after dehydrogenating the first interlayer dielectric layer, wherein the capping layer obstructs or hinders moisture and/or external ions from penetrating into the first interlayer dielectric layer.

10. The method of claim 9, wherein forming the capping layer comprises forming the capping layer in an in-situ process after dehydrogenating the first interlayer dielectric layer.

11. The method of claim 1, further comprising forming a liner layer having a tensile stress on the NMOS transistor before forming the first interlayer dielectric layer.

12. The method of claim 11, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer and the first interlayer dielectric layer is represented by t2, and wherein t2/t1≧

1.14.

13. The method of claim 1, further comprising, after dehydrogenating the first interlayer dielectric layer:

forming an additional interlayer dielectric layer, which has a stress, on the first interlayer dielectric layer; and

dehydrogenating the additional interlayer dielectric layer;

wherein forming the additional interlayer dielectric layer and dehydrogenating the additional interlayer dielectric layer are repeated one or more times.

14. The method of claim 13, wherein dehydrogenating the additional interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or a thermal treatment on the additional interlayer dielectric layer in a dehydrogenation gas atmosphere.

15. The method of claim 14, further comprising forming a liner layer having a tensile stress on the NMOS transistor before forming the first interlayer dielectric layer.

16. The method of claim 15, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer, the dehydrogenated first interlayer dielectric layer, and the dehydrogenated additional interlayer dielectric layer is represented by t3, and wherein t3/t1≧

1.14.

17. The method of claim 1, wherein:

forming the NMOS transistor on the semiconductor substrate comprises forming the NMOS transistor and a PMOS transistor on the semiconductor substrate; and

forming the first interlayer dielectric layer on the NMOS transistor comprises forming the first interlayer dielectric layer on the NMOS transistor and on the PMOS transistor.

18. The method of claim 17, further comprising implanting germanium and/or nitrogen ions into a portion of the first interlayer dielectric layer formed on the PMOS transistor after dehydrogenating the first interlayer dielectric layer.

19. The method of claim 17, further comprising forming a mask pattern on a portion of the first interlayer dielectric layer formed on the PMOS transistor before dehydrogenating the first interlayer dielectric layer.

20. A method of manufacturing a semiconductor device, comprising:

forming an NMOS transistor on a substrate;

forming a first interlayer dielectric layer, which includes an O₃-TEOS layer having a tensile stress, on the NMOS transistor; and

dehydrogenating the first interlayer dielectric layer.

21. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or a thermal treatment on the first interlayer dielectric layer in a dehydrogenation gas atmosphere.

22. The method claim 21, wherein the dehydrogenation gas comprises N₂, O₂, O₃, N₂O, H₂, D₂ and/or a combination thereof.

23. The method of claim 20, wherein the first interlayer dielectric layer has a tensile stress of 200 MPa or more following dehydrogenization.

24. The method of claim 20, further comprising, after forming the first interlayer dielectric layer, forming contacts connected to the NMOS transistor in the first interlayer dielectric layer.

25. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, the method further comprising forming a second interlayer dielectric layer on the dehydrogenated first interlayer dielectric layer, wherein the second interlayer dielectric layer has a stress smaller than a stress of the dehydrogenated first interlayer dielectric layer.

26. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, the method further comprising forming a capping layer on the dehydrogenated first interlayer dielectric layer, wherein the capping layer is configured to obstruct or hinder moisture and/or external ions from penetrating into the dehydrogenated first interlayer dielectric layer.

27. The method of claim 26, wherein forming the capping layer comprises forming the capping layer in an in-situ process after dehydrogenating the first interlayer dielectric layer.

28. The method of claim 20, further comprising, before forming the first interlayer dielectric layer, forming a liner layer having a tensile stress on the NMOS transistor.

29. The method of claim 27, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer and the dehydrogenated first interlayer dielectric layer is represented by t2, and wherein t2/t1≧

1.14.

30. The method of claim 20, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, the method further comprising:

forming an additional interlayer dielectric layer having a tensile stress on the dehydrogenated first interlayer dielectric layer; and

dehydrogenating the additional interlayer dielectric layer;

wherein forming the additional interlayer dielectric layer and dehydrogenating the additional interlayer dielectric layer are repeated one or more times.

31. The method of claim 30, wherein dehydrogenating the additional interlayer dielectric layer comprises performing a plasma treatment, a UV treatment, and/or thermal treatment on the additional interlayer dielectric layer in a dehydrogenation gas atmosphere.

32. The method of claim 31, further comprising, before forming the first interlayer dielectric layer, forming a liner layer having a tensile stress on the NMOS transistor.

33. The method of claim 32, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, wherein dehydrogenating the first interlayer dielectric layer comprises forming a dehydrogenated first interlayer dielectric layer, wherein dehydrogenating the additional interlayer dielectric layer comprises forming a dehydrogenated additional interlayer dielectric layer, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer, the dehydrogenated first interlayer dielectric layer, and the dehydrogenated additional interlayer dielectric layer is represented by t3, and wherein t3/t1≧

1.14.

34. The method of claim 20, wherein:

forming the NMOS transistor on the semiconductor substrate comprises forming the NMOS transistor and a PMOS transistor on the semiconductor substrate; and

forming the first interlayer dielectric layer on the NMOS transistor comprises forming the first interlayer dielectric layer on the NMOS transistor and the PMOS transistor.

35. The method of claim 34, further comprising implanting germanium and/or nitrogen ions into a portion of the first interlayer dielectric layer formed on the PMOS transistor after dehydrogenating the first interlayer dielectric layer.

36. The method of claim 34, further comprising forming a mask pattern on a portion of the first interlayer dielectric layer formed on the PMOS transistor before dehydrogenating the first interlayer dielectric layer.

37. A semiconductor device, comprising:

an NMOS transistor comprising a gate dielectric layer and a gate electrode on a substrate;

a liner layer on the NMOS transistor, the liner layer having a tensile stress; and

a dehydrogenated first interlayer dielectric layer on the liner layer, the dehydrogenated first interlayer dielectric layer having a tensile stress that is increased due to dehydrogenation thereof;

wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer and the dehydrogenated first interlayer dielectric layer is represented by t2, and wherein t2/t1≧

1.14.

38. The device of claim 37, further comprising contacts connected to the NMOS transistor in the dehydrogenated first interlayer dielectric layer.

39. The device of claim 37, wherein the dehydrogenated first interlayer dielectric layer is formed by a plasma treatment, a UV treatment, and/or a thermal treatment in a dehydrogenation gas atmosphere.

40. The device of claim 37, further comprising a second interlayer dielectric layer on the dehydrogenated first interlayer dielectric layer, the second interlayer dielectric layer having a tensile stress smaller than the tensile stress of the dehydrogenated first interlayer dielectric layer.

41. The device of claim 37, further comprising a capping layer on the dehydrogenated first interlayer dielectric layer, the capping layer configured to obstruct or hinder moisture and/or external ions from penetrating into the dehydrogenated first interlayer dielectric layer.

42. The device of claim 41, wherein the capping layer comprises an in-situ capping layer on the dehydrogenated first interlayer dielectric layer.

43. The device of claim 37, further comprising:

a dehydrogenated additional interlayer dielectric layer on the dehydrogenated first interlayer dielectric layer, the dehydrogenated additional interlayer dielectric layer having a tensile stress which is increased due to dehydrogenation of the dehydrogenated additional interlayer dielectric layer,

wherein a total thickness of the liner layer, the dehydrogenated first interlayer dielectric layer, and the dehydrogenated additional interlayer dielectric layer is represented by t3, and wherein t3/t1≧

1.14.

44. A semiconductor device, comprising:

an NMOS transistor on a substrate;

a first interlayer dielectric layer on the NMOS transistor, the first interlayer dielectric layer having a tensile stress due to dehydrogenation of the first interlayer dielectric layer; and

a second interlayer dielectric layer on the first interlayer dielectric layer, the second interlayer dielectric layer having a stress smaller than that of the first interlayer dielectric layer.

45. The device of claim 44, wherein the first interlayer dielectric layer is formed by a plasma treatment, a UV treatment, and/or a thermal treatment in a dehydrogenation gas atmosphere.

46. The device of claim 44, further comprising a capping layer on the second interlayer dielectric layer and configured to obstruct or hinder moisture and/or external ions from penetrating into the second interlayer dielectric layer.

47. The method of claim 46, wherein the capping layer comprises an in-situ capping layer on the second interlayer dielectric layer.

48. The device of claim 44, further comprising a liner layer between the NMOS transistor and the first interlayer dielectric layer, the liner layer having a tensile stress.

49. The device of claim 48, wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer and the dehydrogenated first interlayer dielectric layer is represented by t2, and wherein t2/t1≧

1.14.

50. The device of claim 48, further comprising:

an additional interlayer dielectric layer between the first interlayer dielectric layer and the second interlayer dielectric layer, the additional interlayer dielectric layer having a tensile stress which is increased due to dehydrogenation of the additional interlayer dielectric layer,

wherein the NMOS transistor comprises a gate dielectric layer and a gate electrode, and wherein a total thickness of the gate dielectric layer, the gate electrode, and the liner layer of the NMOS transistor is represented by t1 and a total thickness of the liner layer, the dehydrogenated first interlayer dielectric layer, and the dehydrogenated additional interlayer dielectric layer is represented by t3, and wherein t3/t1≧

1.14.

51. A semiconductor device, comprising:

an NMOS transistor and a PMOS transistor on a semiconductor substrate; and

a first interlayer dielectric layer on the NMOS and PMOS transistors,

wherein the first interlayer dielectric layer comprises nitrogen and/or germanium ions implanted into a portion of the first interlayer dielectric layer on the PMOS transistor.

52. The device of claim 51, wherein the first interlayer dielectric layer is formed by a plasma treatment, a UV treatment, and/or a thermal treatment in a dehydrogenation gas atmosphere.

53. The device of claim 51, further comprising a capping layer on the first interlayer dielectric layer, the capping layer configured to obstruct or hinder moisture and/or external ions from penetrating into the first interlayer dielectric layer.

54. The method of claim 53, wherein the capping layer comprises an in-situ capping layer on the dehydrogenated first interlayer dielectric layer.