Flash memory with coding and signal processing

• US 20070171714A1
• Filed: 11/08/2006
• Published: 07/26/2007
• Est. Priority Date: 01/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Pantas, Wu, Zining
• Granted Patent: US 8,055,979 B2
• Time in Patent Office: Days
• US Class Current: 365/185.90
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.

Claims

1. A solid state non-volatile memory unit comprising:

a first encoder;

a multi-level solid state non-volatile memory array adapted to store data encoded by the first encoder; and

a first decoder adapted to decode data retrieved from the memory array.

2. The solid state non-volatile memory unit of claim 1 wherein the memory array is a flash EEPROM array.

3. The solid state non-volatile memory unit of claim 1 further comprising:

a second encoder in communication with the first encoder; and

a second decoder in communication with the first decoder.

4. The solid state non-volatile memory unit of claim 3 wherein the first encoder is adapted to execute a first ECC different from a second ECC executed by the second encoder.

5. The solid state non-volatile memory unit of claim 3 wherein the second encoder comprises a Reed-Solomon encoder.

6. The solid state non-volatile memory unit of claim 1 further comprising:

a modulator adapted to modulate the encoded data; and

a demodulator adapted to demodulate the modulated data retrieved from the memory array.

7. The solid state non-volatile memory unit of claim 1 wherein said first encoder is a binary encoder.

8. The solid state non-volatile memory unit of claim 7 wherein said binary encoder encodes in accordance with a binary code selected from a group consisting of Hamming code. BCH code, Reed-Muller code and Array Code.

9. The solid state non-volatile memory unit of claim 1 wherein said first encoder is selected from a group consisting of non-binary encoder and convolutional encoder.

10. The solid state non-volatile memory unit of claim 1 wherein said first encoder is disposed in a trellis-coded modulator.

11. The solid state non-volatile memory unit of claim 1 wherein said first encoder is an iterative encoder.

12. The solid state non-volatile memory unit of claim 11 wherein said iterative encoder encodes in accordance with a code selected from a group consisting of low-density parity check code and Turbo code.

13. The solid state non-volatile memory unit of claim 11 wherein said iterative encoder is a symbol-based iterative encoder.

14. The solid state non-volatile memory unit of claim 1 wherein the solid state non-volatile memory unit is disposed in an integrated circuit.

15. A method of operating a solid state non-volatile memory unit, the method comprising:

encoding a first data;

storing the encoded first data in a multi-level solid state non-volatile memory array;

retrieving the first encoded data from the memory array; and

decoding the first data retrieved from the memory array.

16. The method of claim 15 wherein the memory array is a flash EEPROM array.

17. The method of claim 15 further comprising:

encoding a second data to generate the first data; and

decoding the decoded first data to generate the second data.

18. The method of claim 17 wherein the encoding of the first data is performed in accordance with a first ECC different from a second ECC in accordance with which the second data is encoded.

19. The method of claim 18 wherein the second ECC is a Reed-Solomon code.

20. The method of claim 15 further comprising:

modulating the encoded data;

storing the modulated data in the memory array;

retrieving the modulated data from the memory array; and

demodulating the data retrieved from the memory array.

21. The method of claim 15 further comprising:

encoding the first data in accordance with a binary code.

22. The method of claim 21 wherein said binary code is selected from a group consisting of Hamming code, BCH code, Reed-Muller code and Array Code.

23. The method of claim 15 further comprising:

encoding the first data in accordance with one of non-binary code and convolutional code.

24. The method of claim 20 wherein said encoding comprises trellis-coded modulation.

25. The method of claim 15 wherein said encoding is an iterative encoding.

26. The method of claim 25 wherein said iterative encoding is performed in accordance with a code selected from a group consisting of low-density parity check code and Turbo code.

27. The method of claim 25 wherein said iterative encoding is a symbol-based iterative encoding.

28. A solid state non-volatile memory unit comprising:

means for encoding a first data;

means for storing the encoded first data in a multi-level solid state non-volatile memory array;

means for retrieving the first encoded data from the memory array; and

means for decoding the first data retrieved from the memory array.

29. The solid state non-volatile memory unit of claim 28 wherein the memory array is a flash EEPROM array.

30. The solid state non-volatile memory unit of claim 28 further comprising:

means for encoding a second data to generate the first data; and

means for decoding the decoded first data to generate the second data.

31. The solid state non-volatile memory unit of claim 30 wherein the means for encoding the first data is adapted to execute a first ECC different from a second ECC executed by the means for encoding the second data.

32. The solid state non-volatile memory unit of claim 31 wherein the second ECC is a Reed-Solomon code.

33. The solid state non-volatile memory unit of claim 28 further comprising:

means for modulating the encoded data;

means for storing the modulated data in the memory array;

means for retrieving the modulated data from the memory array; and

means for demodulating the data retrieved from the memory array.

34. The solid state non-volatile memory unit of claim 28 wherein the means for encoding the first data encodes in accordance with a binary code.

35. The solid state non-volatile memory unit of claim 34 wherein the means for encoding the first data encodes in accordance with a binary code selected from a group consisting of Hamming code,. BCH code,. Reed-Muller code and Array Code.

36. The solid state non-volatile memory unit of claim 28 wherein said means for encoding the first data is selected from a group consisting of non-binary encoder and convolutional encoder.

37. The solid state non-volatile memory unit of claim 33 wherein said means for encoding the first data is disposed in a trellis-coded modulator.

38. The solid state non-volatile memory unit of claim 28 wherein said means for encoding the first data is an iterative encoder.

39. The solid state non-volatile memory unit of claim 38 wherein said iterative encoder encodes in accordance with a code selected from a group consisting of low-density parity check code and Turbo code.

40. The solid state non-volatile memory unit of claim 38 wherein said iterative encoder is a symbol-based iterative encoder.