DRAM (DYNAMIC RANDOM ACCESS MEMORY) CELLS
3 Assignments
0 Petitions
Accused Products
Abstract
A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.
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Citations
26 Claims
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1-14. -14. (canceled)
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15. A semiconductor fabrication method, comprising:
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providing a semiconductor structure which includes;
(a) a semiconductor substrate, (b) a trench in the semiconductor substrate, wherein the trench comprises a side wall and a bottom wall, and wherein the side wall comprises an upper side wall portion and a lower side wall portion;
forming a first doped semiconductor region and a second doped semiconductor region, wherein the first doped semiconductor region (i) wraps around the lower side wall portion of the trench and (ii) abuts the bottom wall and the lower side wall portion of the trench, wherein the second doped semiconductor region wraps around and abuts the upper side wall portion of the trench, wherein the second doped semiconductor region is self-aligned to the first doped semiconductor region, wherein the first doped semiconductor region comprises dopants electrically exhibiting a first doping polarity, wherein the second doped semiconductor region comprises dopants electrically exhibiting a second doping polarity which is opposite to the first doping polarity, and after said forming the first doped semiconductor region and the second doped semiconductor region is performed, forming a dielectric layer and an electrically conducting region in the trench, wherein the dielectric layer is on the side wall and the bottom wall of the trench, wherein the dielectric layer comprises a capacitor dielectric portion and a collar dielectric portion, wherein the electrically conducting region comprises dopants of the first doping polarity, wherein the electrically conducting region comprises a first portion, a second portion, and a third portion, wherein the second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion, and wherein when going from an interfacing surface of the collar dielectric portion and the second doped semiconductor region and away from the collar dielectric portion, a doping concentration of the second doped semiconductor region decreases. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26-30. -30. (canceled)
Specification