APPARATUS AND METHOD FOR CHECKING AN ERROR DETECTION FUNCTIONALITY OF A DATA PROCESSOR

• US 20070277070A1
• Filed: 01/12/2007
• Published: 11/29/2007
• Est. Priority Date: 01/13/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Janke, Marcus, Laackmann, Peter
• Granted Patent: US 8,918,679 B2
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/77 in smart cards

Abstract

An apparatus for checking an error detection functionality of a data processing circuit, comprising an arithmetic logic unit, which provides an output datum based on an input datum, and an error detection circuit that executes the error detection functionality and detects an error based on the output datum during correct execution of the error detection functionality, and generates an error signal, if an error is present, which comprises a control circuit that passes the error signal through to an error signal output in a normal operating mode, and blocks the error signal in a checking mode, does not let the error signal pass to the error signal output, influences the arithmetic logic unit, the error detection circuit or the input datum such that the error detection circuit detects an error during correct execution of the error detection functionality, and, if no error signal is received in response to influencing, outputs an alarm signal indicating an incorrect execution of the error detection functionality.

Claims

1. An apparatus for checking an error detection functionality of a data processor having an arithmetic logic unit that provides an output datum based on an input datum, and an error detector that executes the error detection functionality and detects an error during correct execution of the error detection functionality based on the output datum, and, if an error is present, generates an error signal, comprising:

a controller that passes the error signal through to an error signal output in a normal operating mode, and blocks the error signal in a checking mode, in order to not let the error signal pass through to the error signal output, influences the arithmetic logic unit, the error detector or the input datum such that the error detector detects an error during correct execution of the error detection functionality, and, if no error signal is received in response to influencing, does not output an alarm signal indicating an incorrect execution of the error detection functionality.

2. The apparatus according to claim 1, wherein the error detector additionally detects a presence of an error based on the input datum.

3. The apparatus according to claim 1, wherein the data processor comprises a further arithmetic logic unit that provides a further output datum based on a further input datum, and wherein the error detector additionally detects a presence of an error based on the further output datum.

4. The apparatus according to claim 3, wherein the controller further influences the further arithmetic logic unit or the further input datum, to cause an error during correct execution of the error detection functionality by the error detector.

5. The apparatus according to claim 1, wherein the error detector infers an error when the output datum fulfills a predetermined condition.

6. The apparatus according to claim 1, wherein the error detector infers an error when the output datum and the input datum do not have a predetermined relation to each other.

7. The apparatus according to claim 1, wherein the error detector infers an error when a datum or a plurality of data of a group of the data do not have a predetermined relation to each other, wherein the group of data comprises the output datum, the further output datum, the input datum and the further input datum.

8. The apparatus according to claim 1, wherein the controller changes to the checking mode, when a predetermined trigger condition is fulfilled, and switches to the normal operating mode, when the predetermined trigger condition is not fulfilled.

9. The apparatus according to claim 8, wherein the predetermined trigger condition is intermittently fulfilled.

10. The apparatus according to claim 1, wherein the controller further causes the error detector without influencing to check the output datum with regard to an error, after receiving the error signal in response to influencing, and to output the alarm signal, if the controller receives a further error signal from the error detector.

11. A method for checking an error detection functionality of a data processor with an arithmetic logic unit, which provides an output datum based on an input datum, and an error detector, which performs the error detection functionality and detects an error based on the output datum during correct execution of the error detection functionality, and, if an error is present, generates an error signal, comprising:

in a normal operating mode;

passing the error signal through to an error signal output;

in a checking mode;

blocking the error signal to not let the error signal pass through to the error signal output;

influencing the arithmetic logic unit, the error detector or the input datum, such that the error detector detects an error during correct execution of the error detection functionality; and

outputting an alarm signal indicating an incorrect execution of the error detection functionality, if the error detector does not output an error signal.

12. A program with program code for performing the method for checking an error detection functionality of a data processor with an arithmetic logic unit, which provides an output datum based on an input datum, and an error detector, which performs the error detection functionality and detects an error based on the output datum during correct execution of the error detection functionality, and, if an error is present, generates an error signal, comprising:

in a normal operating mode;

passing the error signal through to an error signal output;

in a checking mode;

blocking the error signal to not let the error signal pass through to the error signal output;

influencing the arithmetic logic unit, the error detector or the input datum, such that the error detector detects an error during correct execution of the error detection functionality; and

outputting an alarm signal indicating an incorrect execution of the error detection functionality, if the error detector does not output an error signal,

when the program runs on a processor.

13. A data processor comprising:

an arithmetic logic unit that provides an output datum based on an input datum;

an error detector that executes an error detection functionality of the data processor and detects an error during correct execution of the error detection functionality based on the output datum, and, if an error is present, generates an error signal; and

a control means for passing the error signal through to an error signal output in a normal operating mode, and for blocking the error signal in a checking mode, in order to not let the error signal pass through to the error signal output, for influencing the arithmetic logic unit, the error detector or the input datum such that the error detector detects an error during correct execution of the error detection functionality, and, if no error signal is received in response to influencing, does not output an alarm signal indicating an incorrect execution of the error detection functionality.