DYNAMIC RAM STORAGE TECHNIQUES

• US 20070285979A1
• Filed: 08/24/2007
• Published: 12/13/2007
• Est. Priority Date: 03/10/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Turner, John
• Granted Patent: US 7,602,634 B2
• Time in Patent Office: Days
• US Class Current: 365/174
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the chip. Data stored in DRAM cells is provided directly to the pass gates at the full supply voltage to prevent signal degradation. A p-channel transistor eliminates all N-type junctions from the storage node reducing the collection of particles that may cause soft errors.

Claims

1. A DRAM cell having minimal soft errors, comprising:

an n-channel first transistor having a gate coupled to a read word line and a drain coupled to a read bit line;

an inverter having an output coupled to a source of the n-channel transistor;

a p-channel transistor coupled between the inverter and a write bit line, a gate of the third transistor being coupled to a write word line; and

a pass gate coupled between the n-channel transistor and an input of the inverter such that a voltage stored on the inverter is operable to drive a gate voltage of the pass gate.

2. The DRAM cell according to claim 1, wherein the pass gate is a programmable routing connector that couples interconnect lines on a field programmable gate array.

3. The DRAM cell according to claim 1, wherein the pass gate is used to configure logic performed by logic circuitry on a field programmable gate array.

4. The DRAM cell according to claim 1, wherein the pass gate is turned fully on or fully off in order to prevent signal degradation.

5. The DRAM cell according to claim 1, wherein at least one refresh cycle is used to maintain a voltage stored at an input of the inverter.

6. The DRAM cell according to claim 1, wherein the inverter is a CMOS inverter.

7. The DRAM cell according to claim 6, wherein the inverter further includes a second p-channel transistor and a second n-channel transistor.

8. The DRAM cell according to claim 7, wherein the second p-channel and second n-channel transistor in the inverter store charge between refresh cycles.

9. The DRAM cell according to claim 1, wherein the input of the inverter is not directly connected to an N-type doped semiconductor region.

10. A method for controlling programmable interconnects and logic functions with minimal soft errors, the method comprising:

applying a first voltage on a write word line to turn on a p-channel transistor;

applying a second voltage on a write bit line coupled to a drain of the p-channel transistor to store charge at an inverter;

applying a third voltage on the write word line to turn off the p-channel transistor; and

driving a gate voltage of a pass gate using the charge stored on the inverter.

11. The method according to claim 10, further comprising:

applying a fourth voltage on a read word line to turn on the n-channel transistor, the second transistor coupled in series with third transistor; and

sensing a fifth voltage on a read bit line coupled to a drain of the n-channel transistor.

12. The method according to claim 10, further comprising:

turning the pass gate fully on or fully off in order to prevent signal degradation.

13. The method according to claim 10, further comprising:

using at least one refresh cycle to maintain a voltage stored at an input of the inverter.

14. A DRAM cell having minimal soft errors, comprising:

an n-channel transistor having a gate coupled to a read word line and a drain coupled to a read bit line;

a single inverter having an output coupled to a source of the first transistor; and

a p-channel transistor coupled between an input of the single inverter and a write bit line, a gate of the p-channel transistor being coupled to a write word line.

15. The DRAM cell according to claim 14, wherein the output of the inverter is coupled to a pass gate.

16. The DRAM cell according to claim 14, wherein the input of the inverter is not directly connected to an N-type doped semiconductor region.

17. The DRAM cell according to claim 14, further comprising a capacitor coupled to the input of the inverter.

18. The DRAM cell according to claim 17, wherein the capacitor is one of a planar capacitor and a trench capacitor.

19. The DRAM cell according to claim 14, further comprising:

a sense amplifier having an input coupled to the read bit line; and

a multiplexer coupled between an output of the sense amplifier and the write bit line.

20. The DRAM cell according to claim 15, wherein the pass gate is a programmable routing connector that couples interconnect lines on a field programmable gate array.

21. The DRAM cell according to claim 15, wherein the pass gate is used to configure logic performed by logic circuitry on a field programmable gate array.

22. The DRAM cell according to claim 14, wherein the single inverter further includes a second p-channel transistor and a second n-channel transistor.