DYNAMIC RAM STORAGE TECHNIQUES
First Claim
1. A DRAM cell having minimal soft errors, comprising:
- an n-channel first transistor having a gate coupled to a read word line and a drain coupled to a read bit line;
an inverter having an output coupled to a source of the n-channel transistor;
a p-channel transistor coupled between the inverter and a write bit line, a gate of the third transistor being coupled to a write word line; and
a pass gate coupled between the n-channel transistor and an input of the inverter such that a voltage stored on the inverter is operable to drive a gate voltage of the pass gate.
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Abstract
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the chip. Data stored in DRAM cells is provided directly to the pass gates at the full supply voltage to prevent signal degradation. A p-channel transistor eliminates all N-type junctions from the storage node reducing the collection of particles that may cause soft errors.
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Citations
22 Claims
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1. A DRAM cell having minimal soft errors, comprising:
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an n-channel first transistor having a gate coupled to a read word line and a drain coupled to a read bit line;
an inverter having an output coupled to a source of the n-channel transistor;
a p-channel transistor coupled between the inverter and a write bit line, a gate of the third transistor being coupled to a write word line; and
a pass gate coupled between the n-channel transistor and an input of the inverter such that a voltage stored on the inverter is operable to drive a gate voltage of the pass gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for controlling programmable interconnects and logic functions with minimal soft errors, the method comprising:
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applying a first voltage on a write word line to turn on a p-channel transistor;
applying a second voltage on a write bit line coupled to a drain of the p-channel transistor to store charge at an inverter;
applying a third voltage on the write word line to turn off the p-channel transistor; and
driving a gate voltage of a pass gate using the charge stored on the inverter. - View Dependent Claims (11, 12, 13)
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14. A DRAM cell having minimal soft errors, comprising:
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an n-channel transistor having a gate coupled to a read word line and a drain coupled to a read bit line;
a single inverter having an output coupled to a source of the first transistor; and
a p-channel transistor coupled between an input of the single inverter and a write bit line, a gate of the p-channel transistor being coupled to a write word line. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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Specification