Printed, self-aligned, top gate thin film transistor

• US 20070287237A1
• Filed: 06/12/2007
• Published: 12/13/2007
• Est. Priority Date: 06/12/2006
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Rockenberger, Joerg, Kamath, Arvind, Cleeves, James
• Granted Patent: US 8,796,125 B2
• Time in Patent Office: Days
• US Class Current: 438/163
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/7866 Non-monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

Claims

1. A method of forming a thin film transistor (TFT), comprising:

a) forming a semiconductor thin film layer;

b) printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT;

c) forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and

d) diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

2. The method of claim 1, wherein forming the semiconductor thin film layer comprises printing a liquid-phase ink comprising a semiconductor-containing precursor onto a substrate.

3. The method of claim 1, wherein the doped glass pattern is printed onto or over regions of the semiconductor thin film layer corresponding to source and drain terminals of the TFT.

4. The method of claim 1, comprising forming the gate dielectric film on an entire surface of the semiconductor thin film layer, then printing a doped glass pattern thereon.

5. The method of claim 4, comprising forming the gate conductor on the gate dielectric film, at least in the gap.

6. The method of claim 5, wherein forming the gate conductor comprises printing an ink comprising a gate conductor precursor on the gate dielectric film.

7. The method of claim 1, comprising printing the doped glass pattern on the semiconductor thin film layer, then forming the gate dielectric film on at least an exposed surface of the semiconductor thin film layer in the gap.

8. The method of claim 1, wherein diffusing the dopant comprises heating the doped glass pattern and the semiconductor thin film layer to a temperature and for a length of time sufficient to form a source/drain structure in the semiconductor thin film layer.

9. The method of claim 1, wherein the step of printing the doped glass pattern comprises printing an ink comprising a doped glass precursor on or over the semiconductor thin film layer, then converting the doped glass precursor ink to a doped glass.

10. The method of claim 1, further comprising removing at least portions of the doped glass pattern, sufficiently to expose surfaces of the semiconductor thin film layer containing diffused dopant.

11. The method of claim 10, wherein removing portions of the doped glass pattern leaves remaining portions of the doped glass pattern.

12. The method of claim 10, further comprising forming a conductive interconnect structure on the exposed surfaces of the semiconductor thin film layer containing diffused dopant.

13. The method of claim 10, further comprising forming an interlayer dielectric film over the doped glass pattern and the gate electrode.

14. The method of claim 1, further comprising forming a passivation layer or a dopant-depleted layer on an exposed surface of the doped glass pattern.

15. A thin film transistor (TFT), comprising:

a) a semiconductor thin film layer;

b) at least part of a doped glass pattern thereon, wherein at least two portions of the doped glass pattern define a gap over a channel region of the TFT;

c) a gate electrode on or over a channel region of the semiconductor thin film layer, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and

d) dopant-containing regions in the semiconductor thin film layer on opposed sides of the channel region.

16. The TFT of claim 15, comprising a plurality of the semiconductor thin film layers, in a transistor body pattern on a substrate.

17. The TFT of claim 15, wherein the doped glass pattern is on or over source and drain regions of the semiconductor thin film layer.

18. The TFT of claim 15, wherein the gate dielectric film is on part of a surface of the semiconductor thin film layer other than in the gap.

19. The TFT of claim 15, wherein the gate electrode fills the gap.

20. The TFT of claim 15, wherein the gate dielectric film comprises a thermal oxide of the semiconductor thin film layer.

21. The TFT of claim 15, wherein the doped glass pattern is on the semiconductor thin film layer, and the gate dielectric film is only in the gap.

22. The TFT of claim 15, wherein the gate conductor comprises a metal.

23. The TFT of claim 15, wherein the dopant of the dopant-containing regions is identical to the dopant of the doped glass pattern.

24. The TFT of claim 15, further comprising a plurality of openings in the doped glass pattern, exposing surfaces of the dopant-containing regions of the semiconductor thin film layer.

25. The TFT of claim 15, further comprising a conductive interconnect structure on the exposed surfaces of the dopant-containing regions of the semiconductor thin film layer.

26. The TFT of claim 15, further comprising an interlayer dielectric film over the doped glass pattern and the gate electrode.

27. The TFT of claim 15, further comprising a passivation layer on or a dopant-depleted layer in an exposed surface of the doped glass pattern.

28. The TFT of claim 15, wherein each interface between an individual dopant-containing region and the channel region is substantially aligned with an edge of the doped glass pattern.