FLEXIBLE METHOD FOR PROCESSING DATA PACKETS IN A NETWORK ROUTING SYSTEM FOR ENHANCED EFFICIENCY AND MONITORING CAPABILITY
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Accused Products
Abstract
According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.
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Citations
47 Claims
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1-27. -27. (canceled)
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28. A data packet processor, comprising:
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An input port for receiving data packets;
a microprocessor for processing packet information from the data packets, the microprocessor comprising;
a plurality of registers each assigned to store packet information of the data packets;
an arithmetic logic unit, configured to perform an arithmetic or logic operation on one or more operands to provide a result of the operation, wherein the operation is selected from the group consisting of an inline rotate operation and a mask operation;
a register select circuit, configured to select the content of a selected one of registers as one of the operands; and
a feedback select circuit, configured to provide the result of the operation as one of the operands. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36)
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37. A method for processing data packets, comprising:
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(a) receiving the data packets from an input port;
(b) processing packet information from the data packets, comprising;
(i) assigning a plurality of registers for storing packet information of the data packets;
(ii) storing the packet information in the registers;
(iii) using a register selection circuit, selecting the content of a selected one of registers as one of a plurality of operands; and
(iv) performing in an arithmetic logic unit an arithmetic or logic operation on the operands to provide a result of the operation; and
(v) feeding back to the register selection circuit the result of the operation to be stored in one of the registers as one of the operands; and
(c) forming CAM lookup targets from the packet information. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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Specification