Flexible method for processing data packets in a network routing system for enhanced efficiency and monitoring capability

• US 7,830,884 B2
• Filed: 09/12/2007
• Issued: 11/09/2010
• Est. Priority Date: 05/06/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks LLC (Broadcom, Inc.)
• Inventors: Davis, Ian Edward
• Primary Examiner(s): Kumar; Pankaj
• Assistant Examiner(s): Jones; Prenell P
• Application Number:
  US11/854,486
• Publication Number:
  US 20080002707A1
• Time in Patent Office: 1,154 Days
• Field of Search: 370/392, 370/389, 370/396, 370/393, 370/401, 370/474, 370/469, 370/360, 370/395, 370/400, 370/398, 370/397, 709/240, 709/223, 709/224
• US Class Current: 370/392
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 45/16 Multipoint routing
• CPC Class Codes: H04L 45/302 Route determination based on requested QoS
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/22 Traffic shaping
• CPC Class Codes: H04L 47/2408 for supporting different services, e.g. a differentiated services [DiffServ] type of service
• CPC Class Codes: H04L 47/39 Credit based

Abstract

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

Claims

1. A data packet processor, comprising:

an input port for receiving data packets; and

a microprocessor for processing packet information from the data packets, the microprocessor comprising;

a plurality of registers each assigned to store packet information of the data packets;

an arithmetic logic unit, configured to perform an arithmetic or logic operation on one or more operands to provide a result of the operation, wherein the operation is selected from a group consisting of an inline rotate operation and a mask operation;

a register select circuit, configured to select content of a selected one of the plurality of registers as one of the operands; and

a feedback select circuit, configured to provide the result of the operation as one of the operands.

2. A data packet processor as in claim 1, wherein the microprocessor comprises a RISC processor.

3. A data packet processor as in claim 1, wherein the arithmetic logic unit is configured also to perform anyone of an and operation, an or operation, an xor operation, a neg operation, an add operation, and a compare operation.

4. A data packet processor as in claim 1, further comprising a content-addressable memory (CAM) lookup handler receiving the contents of the registers, the CAM lookup handler configured to submit CAM requests to a CAM.

5. A data packet processor as in claim 4, wherein the content of one of the registers is selected from a group consisting of a packet header field, a L2 content addressable memory (CAM) lookup target, a L3 CAM lookup target, and a L4 CAM lookup target.

6. A data packet processor as in claim 1, further comprising a parameter memory accessed by the microprocessor for data packet routing parameters in the parameter memory.

7. A data packet processor as in claim 6, further comprising an aging random access memory (RAM) for monitoring aging of the data packet routing parameters.

8. A data packet processor as in claim 1, further comprising a port tracker which receives the data packets from the input port prior to the microprocessor receiving the packet information from the data packets.

9. A data packet processor as in claim 1, wherein the port tracker examines packet contexts of the data packets.

10. A method for processing data packets, comprising:

(a) receiving the data packets from an input port;

(b) processing packet information from the data packets, comprising;

(i) assigning a plurality of registers for storing packet information of the data packets;

(ii) storing the packet information in the registers;

(iii) using a register selection circuit, selecting content of a selected one of registers as one of a plurality of operands;

(iv) performing in an arithmetic logic unit an arithmetic or logic operation on the operands to provide a result of the operation; and

(v) storing the result of the operation in one of the plurality of registers; and

(c) forming CAM lookup targets in one or more registers of the plurality of registers, each CAM lookup target determined based upon the packet information;

wherein the contents of one of the registers is selected from a group consisting of a packet header field, a L2 content addressable memory (CAM) lookup target, a L3 CAM lookup target, and a L4 CAM lookup target.

11. A method as in claim 10, further comprising:

performing a CAM lookup using a CAM lookup target; and

creating a portion of a packet header from the packet information and a result of the CAM lookup.

12. A method as in claim 10, further including storing said packet header in a buffer.

13. A method as in claim 10, further comprising:

receiving the contents of the plurality of registers into a content-addressable memory (CAM) lookup handler; and

submitting from the CAM lookup handler a CAM request to a CAM, the CAM request being composed based in part on the contents of the plurality of registers.

14. A method as in claim 10, further comprising:

performing a type of service field lookup; and

storing said packet information in a buffer.

15. A method as in claim 10, further including accessing parameters from a parameter memory, said parameters chosen from a group consisting of switching parameters and routing parameters.

16. A method as in claim 15, further comprising monitoring aging of the parameters in an aging random access memory (RAM).

17. A method as in claim 10, further comprising processing the data packets for packet contexts in a port tracker prior to processing the packet information.

18. A method as in claim 17, wherein the processing in the port tracker prepares, for each packet, a packet status word including information derived from a header of the data packet.

19. A method as in claim 10, wherein the operation is selected from a group consisting of an and operation, an or operation, an xor operation, a neg operation, an add operation, and a compare operation.

20. A method for processing data packets, comprising:

receiving the data packets from an input port;

processing packet information from the data packets, the processing comprising;

(i) assigning a plurality of registers for storing packet information of the data packets;

(ii) storing the packet information in the registers;

(iii) using a register selection circuit, selecting content of a selected one of registers as one of a plurality of operands;

(iv) performing in an arithmetic logic unit an arithmetic or logic operation on the operands to provide a result of the operation; and

(v) storing the result of the operation in one of the plurality of registers;

forming CAM lookup targets in one or more registers of the plurality of registers, each CAM lookup target determined based upon the packet information;

receiving the contents of the plurality of registers into a content-addressable memory (CAM) lookup handler; and

submitting from the CAM lookup handler a CAM request to a CAM, the CAM request being composed based in part on the contents of the plurality of registers.

21. The method of claim 20 further comprising:

processing the data packets for packet contexts in a port tracker prior to processing the packet information, wherein the processing in the port tracker prepares, for each packet, a packet status word including information derived from a header of the data packet.

22. The method of claim 20 further comprising:

performing a CAM lookup using a CAM lookup target; and

creating a portion of a packet header from the packet information and a result of the CAM lookup.

23. The method of claim 20 further comprising:

performing a type of service field lookup; and

storing said packet information in a buffer.

24. The method of claim 20 further comprising:

accessing parameters from a parameter memory, said parameters chosen from a group consisting of switching parameters and routing parameters; and

monitoring aging of the parameters in an aging random access memory (RAM).

25. The method of claim 20, wherein the operation is selected from a group consisting of an and operation, an or operation, an xor operation, a neg operation, an add operation, or a compare operation.

26. A method for processing data packets, comprising:

receiving the data packets from an input port;

processing the data packets for packet contexts in a port tracker, wherein the processing in the port tracker prepares, for each packet, a packet status word including information derived from a header of the data packet;

after processing the data packets for packet contexts, processing packet information from the data packets, comprising;

(i) assigning a plurality of registers for storing packet information of the data packets;

(ii) storing the packet information in the registers;

(iii) using a register selection circuit, selecting content of a selected one of registers as one of a plurality of operands;

(iv) performing in an arithmetic logic unit an arithmetic or logic operation on the operands to provide a result of the operation; and

(v) storing the result of the operation in one of the plurality of registers; and

forming CAM lookup targets in one or more registers of the plurality of registers, each CAM lookup target determined based upon the packet information.

27. The method of claim 26 further comprising:

performing a CAM lookup using a CAM lookup target; and

creating a portion of a packet header from the packet information and a result of the CAM lookup.

28. The method of claim 26 further comprising:

performing a type of service field lookup; and

storing said packet information in a buffer.

29. The method of claim 26 further comprising:

accessing parameters from a parameter memory, said parameters chosen from a group consisting of switching parameters and routing parameters; and

monitoring aging of the parameters in an aging random access memory (RAM).

30. The method of claim 26 wherein the operation is selected from a group consisting of an and operation, an or operation, an xor operation, a neg operation, an add operation, and a compare operation.