LOW OUTPUT SKEW DOUBLE DATA RATE SERIAL ENCODER

• US 20080036631A1
• Filed: 08/08/2006
• Published: 02/14/2008
• Est. Priority Date: 11/24/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Musfeldt, Curtis Drew
• Granted Patent: US 8,723,705 B2
• Time in Patent Office: Days
• US Class Current: 341/101
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate.

Claims

1. A serial encoder, comprising:

a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output;

a plurality of data input flip-flops coupled to the data inputs of the multiplexer;

a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and

a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit substantially eliminates any output glitches from the output of the multiplexer.

2. An encoder according to claim 1, wherein the multiplexer has eight data inputs and three select inputs.

3. An encoder according to claim 1, wherein the multiplexer is a non-glitchless multiplexer.

4. An encoder according to claim 1, wherein the data input flip-flops and the select input flip-flops are D flip-flops.

5. An encoder according to claim 1, wherein the select inputs of the multiplexer are provided by a counter according to a clock signal.

6. An encoder according to claim 5, wherein the multiplexer outputs a bit at every edge of the clock signal.

7. An encoder according to claim 1, wherein the synchronizing circuit comprises a final data register stage.

8. An encoder according to claim 7, wherein the final data register stage is clock-driven.

9. An encoder according to claim 7, wherein the final data register is separated by a single logic layer from the output of the serial encoder, thereby resulting in a low output skew of the encoder.

10. An encoder according to claim 7, wherein the output of the serial encoder is solely determined by two signals from the final data register stage of the synchronizing circuit, thereby resulting in a low output skew of the encoder.

11. An encoder according to claim 1, wherein the encoder receives a parallel data input and serially outputs the data input onto a serial communications link.

12. An encoder according to claim 11, wherein the serial communications link is a Mobile Display Digital Interface (MDDI) link.

13. An encoder according to claim 1, wherein the synchronizing circuit is implemented using any dual edge flip-flop.

14. A serial encoder, comprising:

means for storing a plurality of data input bits;

means for storing a plurality of select input bits;

means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and

means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output.

15. A serial encoder according to claim 14, wherein said means for eliminating glitches includes a synchronizing circuit.

16. A serial encoder according to claim 14, wherein said serial outputting means outputs a bit at every edge of a clock signal, thereby making the serial encoder a double data rate encoder.

17. A serial encoder according to claim 14, wherein said means for eliminating glitches includes a clock-driven register stage.

18. A serial encoder according to claim 17, wherein said register stage is separated by a single logic layer from the serial encoder output, thereby resulting in a low output skew of the encoder.

19. A serial encoder according to claim 17, wherein the serial encoder output is solely determined by two signals from said register stage, thereby resulting in a low output skew of the encoder.

20. A serial encoder according to claim 14, wherein the encoder receives a parallel data input and serially outputs the data input onto a serial communications link.

21. A serial encoder according to claim 20, wherein the serial communications link is a Mobile Display Digital Interface (MDDI) link.

22. A serial encoder according to claim 14, wherein said means for eliminating glitches includes a dual edge flip-flop.