REDUCING THE TIME TO CONVERT AN ANALOG INPUT SAMPLE TO A DIGITAL CODE IN AN ANALOG TO DIGITAL CONVERTER (ADC)

• US 20080055129A1
• Filed: 11/02/2007
• Published: 03/06/2008
• Est. Priority Date: 07/13/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sinha, Vikas, Pentakota, Visvesvararaya, Udupa, Anand, Oswal, Sandeep, Agarwal, Nitin
• Granted Patent: US 7,576,668 B2
• Time in Patent Office: Days
• US Class Current: 341/123
• CPC Class Codes: H03M 1/168 and delivering the same number of bits

Abstract

A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Claims

1. An analog to digital converter (ADC) comprising:

a first sample and hold amplifier (SHA) receiving an input signal and providing an amplified version of said input signal on a first path;

a second SHA receiving said input signal and also providing an amplified version of said input signal on a second path;

a stage of an ADC generating a sub-code from said input signal, said stage comprising;

a quantizer sampling said input signal on said first path, and generating a sub-code representing a strength of said input signal; and

a first circuit sampling said input signal on said second path, said first circuit generating an amplified residue signal for processing by a next stage also comprised in said ADC.

2. The ADC of claim 1, wherein said quantizer determines said sub-code in a decision duration which overlaps with a duration in which said first circuit performs said sampling.

3. The ADC of claim 2, wherein said quantizer generates said sub-code before said first circuit completes sampling said input signal on said second path.

4. A device comprising:

a processor processing a plurality of digital values; and

an analog to digital converter (ADC) to generate said plurality of digital values, said (ADC) comprising;

a first sample and hold amplifier (SHA) receiving said input signal and providing an amplified version of said input signal on a first path;

a second SHA receiving said input signal and also providing an amplified version of said input signal on a second path;

a quantizer sampling said input signal on said first path, and generating a sub-code representing a strength of said input signal; and

a first circuit sampling said input signal on said second path,

said quantizer and said first circuit being comprised in a stage of said ADC, said first circuit generating an amplified residue signal for processing by a next stage also comprised in said ADC.

5. The device of claim 4, wherein said strength comprises a voltage level.

6. The device of claim 4, wherein said quantizer samples said input signal for a first duration and said first circuit samples said input signal for a second duration, wherein said first duration is less than said second duration.

7. The device of claim 6, wherein said quantizer determines said sub-code in a decision duration which overlaps with said second duration.

8. The device of claim 6, wherein said first circuit comprises a plurality of capacitors, a plurality of switches and an amplifier together sampling said input signal and amplifying a difference of said strength and a voltage equivalent of said sub-code to generate said amplified residue signal.

9. A method of generating a sub-code from an input signal using a stage of an ADC, said method comprising:

amplifying said input signal using two separate amplifiers, wherein the output of a first amplifier is provided on a first path and the output of a second amplifier is provided on a second path, wherein said first amplifier and said second amplifier are comprised in said two separate amplifiers;

generating a sub-code based on a signal received on said first path; and

generating an amplified residue signal for processing by a next stage based on a signal received on said second path, wherein said next stage is also comprised in said ADC.

10. A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.