Memory chip architecture with high speed operation
First Claim
1. A semiconductor memory device comprising:
- at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device;
a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device;
a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and
at least one bank area, arranged between the global line block and the data transmission block, each bank area containing a plurality of data I/O blocks located closer to the data transmission block than the global line blocks and a plurality of control blocks located closer to the global line block than the data transmission block.
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Abstract
A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.
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Citations
10 Claims
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1. A semiconductor memory device comprising:
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at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device;
a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device;
a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and
at least one bank area, arranged between the global line block and the data transmission block, each bank area containing a plurality of data I/O blocks located closer to the data transmission block than the global line blocks and a plurality of control blocks located closer to the global line block than the data transmission block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification