STACKED STRUCTURES AND METHODS OF FABRICATING STACKED STRUCTURES

• US 20080124845A1
• Filed: 11/28/2006
• Published: 05/29/2008
• Est. Priority Date: 11/28/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Wang, Jean, Chiou, Wen-Chih, Wu, Weng-Jin
• Granted Patent: US 7,879,711 B2
• Time in Patent Office: Days
• US Class Current: 438/143
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/14155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/14179 Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/17517 including bump connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/29013 being rectangular or square
• CPC Class Codes: H01L 2224/29035 covering only the peripheral area of the surface to be connected
• CPC Class Codes: H01L 2224/29075 Plural core members
• CPC Class Codes: H01L 2224/29116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/29184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/29186 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/3003 : Layer connectors having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/30155 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/73103 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/049 : Nitrides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/053 : Oxides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10S 438/926 : Dummy metallization

Abstract

A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

Claims

1. A method of forming a semiconductor device, comprising the steps of:

forming at least one transistor gate over a first substrate and at least one first dummy structure within the first substrate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure;

forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer comprising at least one contact structure formed therein and making electrical contact with the transistor gate;

forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure;

bonding the first substrate with a second substrate;

removing at least a portion of the first dummy structure, thereby forming a first opening; and

forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.

2. The method of claim 1, wherein the first dummy structure is formed by a shallow trench isolation process.

3. The method of claim 2, wherein the shallow trench isolation process comprises at least two photolithographic processes and etch processes to form a trench opening for the formation of an isolation structure and an opening for the formation of the first dummy structure.

4. The method of claim 1 further comprising forming at least one etch-stop layer between the first substrate and the ILD layer, wherein the first dummy structure is further formed through the etch-stop layer.

5. The method of claim 1, wherein the first dummy structure is formed only partially through the first substrate, the method further comprising the step of thinning the first substrate to expose a surface of the first dummy structure at a bottom surface of the first substrate.

6. The method of claim 1 further comprising forming at least one inter-metal dielectric (IMD) layer over the ILD layer, the IMD layer including at least one metal-containing layer formed therein, the metal-containing layer making electrical contact with the contact structure and comprising a third conductive structure making electrical contact with the first conductive structure.

7. The method of claim 1 further comprising forming a second pad structure over a bottom surface of the first substrate, the second pad structure making electrical contact with the second conductive structure.

8. The method of claim 1 further comprising forming a second passivation layer over a bottom surface of the first substrate, the second passivation layer comprising at least one second pad structure formed therein and making electrical contact with the conductive structure.

9. The method of claim 1 further comprising:

forming at least one second dummy structure within the first substrate;

removing at least a portion of the second dummy structure to form a second opening; and

forming a conductive material within the second opening for thermal dissipation from a region proximate to a surface of the first substrate to a region proximate to a bottom surface of the first substrate.

10. The method of claim 1 further comprising:

forming a third conductive structure through the first substrate; and

forming at least one second dummy structure between the second conductive structure and the third conductive structure, wherein the second dummy structure reduces electrical coupling between the second and third conductive structures.

11. The method of claim 1 further comprising the step of forming at least one of a dielectric liner and a barrier layer on sidewalls of the first opening.

12. A method of forming a semiconductor device, comprising the steps of:

forming at least one transistor gate over a first substrate and at least one first conductive structure within the first substrate;

forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer comprising at least one contact structure formed therein and making electrical contact with the transistor gate and at least one second conductive structure and making electric contact with the first conductive structure;

forming a first passivation layer over the ILD layer, the first passivation layer comprising at least one first pad structure formed therein, wherein the first pad structure makes electrical contact with the second conductive structure;

bonding the first substrate with a second substrate;

removing at least a portion of the first conductive structure; and

forming a second passivation layer over a bottom surface of the first substrate, the second passivation layer comprising at least one second pad structure formed therein, wherein the second pad structure makes electrical contact with the first conductive structure.

13. A stacked structure, comprising:

at least one first substrate comprising at least one first pad structure formed thereover; and

at least one second substrate comprising;

at least one transistor gate formed over the second substrate and at least one first conductive structure formed through the second substrate;

an interlayer dielectric (ILD) layer formed over the gate transistor, the ILD layer comprising at least one contact structure formed therethrough and making electrical contact with the transistor gate and at least one second conductive structure formed therein at least partially over a surface of the first conductive structure, wherein the top surface of the first conductive structure is substantially planar with a top surface of the second substrate; and

a passivation layer formed over the ILD layer, the passivation layer comprising at least one second pad structure making electrical contact with the second conductive structure, wherein the first substrate is coupled to the second substrate by bonding the first substrate with the second substrate.

14. The stacked structure of claim 13 further comprising at least one etch-stop layer formed between the second substrate and the ILD layer, wherein the first conductive structure is also formed through the etch-stop layer and the top surface of the first conductive structure is substantially planar with a top surface of the etch-stop layer.

15. The stacked structure of claim 13, wherein the first conductive structure comprises at least one of a dielectric liner and a barrier layer surrounding a conductive material.

16. The stacked structure of claim 13 further comprising at least one first dielectric structure formed through the second substrate.

17. The stacked structure of claim 16 further comprising at least one second conductive structure connecting to the first dielectric structure.

18. The stacked structure of claim 13 further comprising at least one second conductive structure connecting to the first conductive structure.

19. The stacked structure of claim 13 further comprising at least one inter-metal dielectric (IMD) layer formed over the ILD layer, the IMD layer including at least one metal-containing layer formed therein, the metal-containing layer making electrical contact with the contact structure and comprising a third conductive structure making electrical contact with the second conductive structure.

20. The stacked structure of claim 13 further comprising a third pad structure formed over a bottom surface of the second substrate, wherein the third pad structure makes electrical contact with the first conductive structure.

21. The stacked structure of claim 20 further comprising a third substrate comprising at least one fourth pad structure, wherein the fourth pad structure is bonded to the third pad structure.

22. The stacked structure of claim 13, wherein the first conductive structure comprises a conductive material surrounded by a dielectric material.

23. The stacked structure of claim 13 further comprising:

at least one third conductive structure formed through the second substrate; and

at least one dielectric structure formed within the second substrate, wherein the dielectric structure is formed between the first conductive structure and the third conductive structure, wherein the second dielectric structure reduces electrical coupling between the second and the third conductive structures.

24. A stacked structure, comprising:

at least one first substrate comprising at least one first pad structure thereover, and

at least one second substrate comprising;

at least one transistor gate formed over the second substrate and a plurality of first conductive structures formed through the second substrate;

an interlayer dielectric (ILD) layer formed over the gate transistor, the ILD layer comprising at least one contact structure formed therein and making electrical contact with the transistor gate and a plurality of second conductive structures formed therethrough at least partially over and making electrical contact with respective ones of the first conductive structures, wherein the top surfaces of the first conductive structures are substantially planar with a top surface of the second substrate; and

at least one dielectric structure formed within the second substrate, wherein the dielectric structure reduces electrical coupling between two adjacent first conductive structures from the plurality of the first conductive structures;

at least one inter-metal dielectric (IMD) layer formed over the ILD layer, the IMD layer including at least one metal-containing layer formed therein, the metal-containing layer making electrical contact with the contact structure and comprising a plurality of third conductive structures making electrical contact with respective ones of the second conductive structures; and

a passivation layer formed over the metal-containing layers, the passivation layer comprising at least one second pad structure formed therethrough and making electrical contact with at least one of the third conductive structures,

wherein the first substrate is coupled to the second substrate by bonding the first substrate with the second substrate.

25. The stacked structure of claim 24, further comprising

a plurality of third pad structures formed over a bottom surface of the second substrate, wherein the third pad structures make electrical contact with respective ones of the first conductive structures;

and

a third substrate comprising a plurality of fourth pad structures, wherein the fourth pad structures are bonded to respective ones of the third pad structures.

26. A stacked structure, comprising:

a first substrate comprising at least one first pad structure over the first substrate and at least one first support structure within and extending above the first substrate, the first pad structure having a first surface, the first support structure having a second surface, wherein the first surface and the second surface are substantially coplanar; and

a second substrate comprising at least one second pad structure over the second substrate and at least one second support structure within and extending above the second substrate, the second pad structure having a third surface, the second support structure having a fourth surface, wherein the third surface contacts the first surface and the fourth surface contacts the second surface.

27. The stacked structure of claim 26 further comprising at least one passivation structure around the stacked structure.

28. The stacked structure of claim 27, wherein the passivation structure comprises at least one dielectric layer.

29. The stacked structure of claim 27, wherein the passivation structure comprises at least one polyimide layer.

30. The stacked structure of claim 26, wherein the first substrate further comprises at least one first protective structure thereover and around the first pad structure and the first support structure, the first protective structure has a fifth surface, the second substrate further comprises at least one second protective structure thereover and around the second pad structure and the second support structure, the second protective structure has a sixth surface, and the sixth surface contacts the fifth surface.

31. The stacked structure of claim 30, wherein the first substrate further comprises at least one third protective structure thereover and around the first pad structure, the first support structure is disposed between the third protective structure and the first protective structure, the third protective structure has a seventh surface, the second substrate further comprises at least one fourth protective structure thereover and around the second pad structure, the second support structure is disposed between the fourth protective structure and the second protective structure, the fourth protective structure has an eighth surface, and the eighth surface contacts the seventh surface.

32. The stacked structure of claim 30, further comprising:

at least one third support structure extending through the first substrate and contacting the first protective structure, and

at least one fourth support structure extending through the second substrate and contacting the second protective structure.

33. The stacked structure of claim 26, wherein the first support structure extends through the first substrate and the second support structure extends through the second substrate.

34. A method of forming a stacked structure, comprising:

forming at least one first pad structure over a first substrate and at least one first support structure through the first substrate, the first pad structure having a first surface, the first support structure having a second surface, wherein the first surface and the second surface are substantially coplanar;

forming at least one second pad structure over a second substrate and at least one second support structure through the second substrate, the second pad structure having a third surface, the second support structure having a fourth surface; and

bonding the first substrate and the second substrate so that the third surface contacts the first surface and the fourth surface contacts the second surface.

35. The method of claim 34, further comprising forming at least one passivation structure around the stacked structure.

36. The method of claim 35, wherein forming the passivation structure comprises forming at least one dielectric layer.

37. The method of claim 35, wherein forming the passivation structure comprises forming at least one polyimide layer.

38. The method of claim 34, further comprising:

forming at least one first protective structure over the first substrate and around the first pad structure and the first support structure, the first protective structure having a fifth surface; and

forming at least one second protective structure over the second substrate and around the second pad structure and the second support structure, the second protective structure having a sixth surface, wherein the sixth surface contacts the fifth surface.

39. The method of claim 38 further comprising:

forming at least one third protective structure over the first substrate and around the first pad structure, the first support structure formed between the third protective structure and the first protective structure, the third protective structure having a seventh surface; and

forming at least one fourth protective structure over the second substrate and around the second pad structure, the second support structure formed between the fourth protective structure and the second protective structure, the fourth protective structure having an eighth surface, wherein the eighth surface contacts the seventh surface.

40. The method of claim 38 further comprising:

forming at least one third support structure extending through the first substrate and contacting the first protective structure; and

forming at least one fourth support structure extending through the second substrate and contacting the second protective structure.