Method and system for creating and programming an adaptive computing engine

• US 20080134108A1
• Filed: 01/25/2008
• Published: 06/05/2008
• Est. Priority Date: 05/13/2002
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L.
• Granted Patent: US 7,865,847 B2
• Time in Patent Office: Days
• US Class Current: 716/2
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system for creating an adaptive computing engine (ACE) includes algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations, and provides mapping of the algorithmic operations to heterogeneous nodes. The mapping is for initially configuring the heterogeneous nodes to provide appropriate hardware circuit functions that perform algorithmic operations. A reconfigurable interconnection network interconnects the heterogeneous nodes. The mapping includes selecting a combination of ACE building blocks from the ACE building block types for the appropriate hardware circuit functions. The system and corresponding method also includes utilizing the algorithmic operations for optimally configuring the heterogeneous nodes to provide the appropriate hardware circuit function. The utilizing includes the simulating of the performance of the ACE with the combination of ACE building blocks and altering the combination until predetermined performance standards that determine the efficiency of the ACE are met while simulating performance of the ACE.

Claims

1. A system for creating an adaptive computing engine (ACE), the system comprising:

algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations;

means for mapping the algorithmic operations to heterogeneous nodes such that the heterogeneous nodes are initially configured to provide appropriate hardware circuit functions that perform the algorithmic operations, the heterogeneous nodes being coupled with each other by a reconfigurable interconnection network, the mapping by the mapping means including selecting a combination of ACE building blocks from ACE building block types for the appropriate hardware circuit functions; and

means for utilizing the algorithmic operations such that the heterogeneous nodes are optimally configured to provide the appropriate hardware circuit functions, the utilizing by the utilizing means including simulating performance of the ACE with the combination of ACE building blocks and altering the combination of ACE building blocks until predetermined performance standards that determine an efficiency of the ACE are met while simulating performance of the ACE.

2. The system of claim 1 wherein the ACE building blocks types include linear computation block types, finite state machine block types, field programmable gate array block types, bit processor block types, and memory block types.

3. The system of claim 1 wherein the mapping means further includes a profiler that comprises:

means for providing code to simulate a hardware design that performs the algorithmic operations; and

means for identifying one or more hot spots in the code, wherein the identified hot spots are those areas of code requiring high power and/or high data movement and the mapping means selects the combination of ACE building blocks based on the identified hot spots.

4. The system of claim 3 wherein each hot spot comprises a computational hot spot or a data movement hot spot.

5. The system of claim 2 wherein the linear computation block types are selected from the group consisting of:

multipliers, adders, double adders, multiply double accumulators, radix 2, DCT, FIR, IIR, FFT, square root, and divides.

6. The system of claim 4 wherein the mapping means uses each data movement hot spot to restrict high data movements to a minimum physical distance in the ACE.

7. A method for creating an adaptive computing engine (ACE), the method comprising:

providing algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations;

mapping the algorithmic operations to heterogeneous nodes such that the heterogeneous nodes are initially configured to provide appropriate hardware circuit functions that perform the algorithmic operations, the heterogeneous nodes being coupled with each other by a reconfigurable interconnection network, the mapping including selecting a combination of ACE building blocks from ACE building block types for the appropriate hardware circuit functions; and

utilizing the algorithmic operations such that the heterogeneous nodes are optimally configured to provide the appropriate hardware circuit functions, the utilizing comprising simulating performance of the ACE with the combination of ACE building blocks and altering the combination of ACE building blocks until predetermined performance standards that determine an efficiency of the ACE are met while simulating performance of the ACE.

8. The method of claim 7 wherein the ACE building blocks types include linear computation block types, finite state machine block types, field programmable gate array block types, bit processor block types, and memory block types.

9. The method of claim 7 wherein the mapping further includes profiling using a profiler, wherein the profiling comprises:

providing code to simulate a hardware design that performs the algorithmic operations; and

identifying one or more hot spots in the code, wherein the identified hot spots are those areas of code requiring high power and/or high data movement and the mapping selects the combination of ACE building blocks based on the identified hot spots.

10. The method of claim 9 wherein each hot spot comprises a computational hot spot or a data movement hot spot.

11. The method of claim 8 wherein the linear computation block types are selected from the group consisting of:

multipliers, adders, double adders, multiply double accumulators, radix 2, DCT, FIR, IIR, FFT, square root, and divides.

12. The method of claim 10 wherein the mapping uses each data movement hot spot to restrict high data movements to a minimum physical distance in the ACE.

13. A method for optimizing operations of an adaptive computing engine (ACE), the method comprising:

providing a plurality of computation unit composite blocks for an adaptive computing engine;

selecting a combination of computation units from the plurality to perform a predetermined function;

simulating performance of the predetermined function by the selected combination;

determining whether the simulated performance meets chosen metrics of performance; and

adjusting the selected combination until the chosen metrics of performance are met.

14. The method of claim 13 wherein the predetermined function further comprises a hot spot portion of a device program.

15. The method of claim 14 further comprising translating the hot spot portion from the programming language of the device program into a language designed for the computation units.

16. The method of claim 13 wherein providing further comprises storing information regarding available computation units in a database.

17. The method of claim 13 wherein determining further comprises determining whether the selected combination meets computation power efficiency metrics.

18. A profiler for an adaptive computing engine (ACE), the profiler comprising:

means for providing code to simulate a hardware design, and

means for identifying one or more hot spots in the code, wherein the identified hot spots are those areas of code requiring high power and/or high data movement.

19. The profiler of claim 18 wherein a hot spot comprises any combination of computational hot spots and data movement hot spots.