Memory array error correction apparatus, systems, and methods
First Claim
1. An apparatus comprising:
- a memory array; and
an error code module coupled to the memory array and including a data buffer having a plurality of data registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles, the error code module operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
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Accused Products
Abstract
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
111 Citations
48 Claims
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1. An apparatus comprising:
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a memory array; and an error code module coupled to the memory array and including a data buffer having a plurality of data registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles, the error code module operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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receiving a plurality of data bursts to be written to a memory array on a corresponding plurality of consecutive clock cycles; and performing a read/modify/write process for each of the plurality of data bursts within a time period no longer than a period of two cycles of the corresponding plurality of consecutive clock cycles. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method comprising:
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receiving a first plurality of data bits following a first clock cycle transition of a plurality of consecutive clock cycle transitions, the first plurality of data bits to be written to at least one portion of a group of data bits stored at a first address in a memory array; and following the first clock cycle transition and before a third clock cycle transition of the plurality of consecutive clock cycle transitions; reading at the first address a first group of stored data bits to generate a first group of read data bits; generating a first group of write data bits by combining the first plurality of data bits with the first group of read data bits; generating a first error correction code for the first group of write data bits; and writing the first group of write data bits to the first address. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method comprising:
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providing a first data burst during a first clock cycle and providing a second data burst during a second and consecutive clock cycle; and within a time period no longer than an interval defined by the first clock cycle and the second clock cycle; providing at a local input/output a first plurality of data bits associated with a wordline and a first plurality of column select lines coupled to an array of memory cells; gating the first plurality of data bits to a global read input/output from the local input/output; clearing the first plurality of data bits from the local input/output after gating the first plurality of data bits to the global read input/output; providing at the local input/output a second plurality of data bits associated with the wordline and a second plurality of column select lines coupled to the array of memory cells; gating the second plurality of data bits to the global read input/output from the local input/output; clearing the second plurality of data bits from the local input/output after gating the second plurality of data bits to the global read input/output; providing a first plurality of write data bits including a plurality of error correction code bits associated with the first plurality of write data bits to a global write input/output; and writing the first plurality of write data bits including the plurality of error correction code bits to the array of memory cells associated with the wordline and the first plurality of column select lines through the local input/output after clearing the second plurality of data bits from the local input/output. - View Dependent Claims (32, 33, 34)
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35. A system comprising:
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a processor coupled to a memory array, the processor operable to provide a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles, and a data mask for each of the plurality of data bursts; and an error code module coupled to the processor and to the memory array, the error code module operable to receive the plurality of data bursts and to perform a read/modify/write process for each of the plurality of data bursts within a time period no longer than a period of two cycles of the plurality of consecutive clock cycles. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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Specification