Method of semiconductor device protection, package of semiconductor device

• US 20080203558A1
• Filed: 04/24/2008
• Published: 08/28/2008
• Est. Priority Date: 10/07/2003
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Maruyama, Shigeyuki, Tashiro, Kazuhiro, Kohashi, Naohito, Fukuda, Keisuke
• Granted Patent: US 7,807,481 B2
• Time in Patent Office: Days
• US Class Current: 257/704
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/67333 Trays for chips magazine for components H05K13/0084
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16153 Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
• CPC Class Codes: H01L 2924/1616 Cavity shape
• CPC Class Codes: H01L 2924/166 Material
• CPC Class Codes: Y10T 29/49826 Assembling or joining

Abstract

A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Claims

1. A method for protecting a semiconductor device, comprising the step of:

attaching a protection member detachably to the semiconductor device that includes one or more elements.

2. A method for protecting a semiconductor device that is subjected to a plurality of treatments after fabrication but before shipment, comprising the step of:

performing the treatments with a protection member being attached to the semiconductor device.

3. The method as claimed in claim 2, wherein

the treatments include transportation of the semiconductor device with the semiconductor device being held by a suction chuck through a suction hole formed on the protection member.

4. A method for testing a semiconductor device, comprising the step of:

attaching a semiconductor device protection cover detachably to the semiconductor device; and

pressing the semiconductor device against an IC contactor with the semiconductor device protection cover therebetween for a test.

5. A semiconductor device packaging structure for packaging a semiconductor device, comprising:

a tray including a first semi-tray and a second semi-tray, the semiconductor device being attached to and packaged in the tray; and

a semiconductor device protection cover arranged between the first semi-tray and a surface of the semiconductor device,

wherein

the semiconductor device protection cover comprises;

a base portion;

a first surface, said first surface being flat; and

a second surface having a projecting portion to be brought into contact with a substrate of the semiconductor device and a depressed portion not to be brought into contact with parts mounted in the semiconductor device.

6. A semiconductor device package structure for packaging a semiconductor device, comprising:

an embossed tape on which the semiconductor device is pasted; and

a semiconductor device protection cover arranged on a surface of the semiconductor device,

wherein

the semiconductor device protection cover comprises;

a base portion;

a first surface, said first surface being flat; and

a second surface having a projecting portion to be brought into contact with a substrate of the semiconductor device and a depressed portion not to be brought into contact with parts mounted in the semiconductor device.