Method and System for Modeling a Bus for a System Design Incorporating One or More Programmable Processors
First Claim
1. A method for processing data through a virtual bus structure model for system designs including one or more programmable processors, the method comprising:
- indicating that a transaction is available for transfer through the virtual bus structure model;
setting a length of a transaction data to be transferred through the virtual bus structure model, wherein the transaction data comprises a specified number of data beats;
dividing the transaction data into one or more data payloads, wherein each data payload has a data payload length;
committing to a transfer of at least one data payload of the transaction data based on the specified number of data beats in the at least one data payload; and
routing the committed at least one data payload through the virtual bus structure model.
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Abstract
Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.
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Citations
30 Claims
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1. A method for processing data through a virtual bus structure model for system designs including one or more programmable processors, the method comprising:
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indicating that a transaction is available for transfer through the virtual bus structure model; setting a length of a transaction data to be transferred through the virtual bus structure model, wherein the transaction data comprises a specified number of data beats; dividing the transaction data into one or more data payloads, wherein each data payload has a data payload length; committing to a transfer of at least one data payload of the transaction data based on the specified number of data beats in the at least one data payload; and routing the committed at least one data payload through the virtual bus structure model. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for processing data in a transaction through a virtual bus structure model for system designs including one or more programmable processors, the virtual bus structure model located between a sender of data and a receiver of data, wherein the sender of data is configured to write data through the transaction and the receiver of data is configured to read data through the transaction, the method comprising:
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(a) determining a number of data beats to commit to supply from a sender of data to a receiver of data; (b) marking a data channel as busy; (c) indicating a simulated time at which the first of the committed data beats will be available from the sender of data; (d) signaling the receiver of data that the number of data beats is available; (e) determining a number of data payloads needed to transfer the number of data beats; (f) determining the point in simulated time at which the last of the data beats will be accepted by the receiver of data; and (g) signaling the sender of data the acceptance of a data payload by the receiver of data. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A system for processing data in a transaction comprising:
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a virtual bus structure model; a data sender device model; a data recipient device model; an indication module configured to indicate that transaction data is available for transfer through the virtual bus structure model from the data sender device model to the data recipient device model; a data payload module configured to set a length of a data payload to be transferred through the virtual bus structure model, wherein the data payload comprises a specified number of data beats, wherein the transaction data is divided into one or more data payloads, each data payload having a data payload length, and wherein the data payload module is configured to commit to a transfer of at least one data payload of the transaction data based on the specified number of data beats in the data payload; and a routing module configured to route the at least one data payload from the data sender device model through the virtual bus structure model to the data recipient device model. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A computer program product comprising a computer usable medium having control logic recorded thereon for enabling a processor to model data flow through a virtual bus structure model for system designs including one or more programmable processors, said control logic comprising:
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first computer readable program code means for enabling the processor to indicate that a transaction is available for transfer through the virtual bus structure model; second computer readable program code means for enabling the processor to set a length of a data payload to be transferred through the virtual bus structure model, wherein the data payload comprises a specified number of data beats; third computer readable program code means for enabling the processor to divide the transaction into one or more data payloads, each data payload having the data payload length; fourth computer readable program code means for enabling the processor to commit to a transfer of at least one data payload of the transaction based on the specified number of data beats in the data payload; and fifth computer readable program code means for enabling the processor to route the at least one data payload through the virtual bus structure model. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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Specification