Reconfigurable computer bus
First Claim
1. A computer bus system, comprising:
- a plurality of modules, each module comprising a processor and a bus controller that manages a communication channel coupling the plurality of modules, where the bus controller employs a reconfigurable protocol to asynchronously communicate with the processors.
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Accused Products
Abstract
A bus system in which a bus controller, such as a complex programmable logic device, manages a communication channel coupling modules which can implement a node in a sensor network and/or an embedded system device. The system abstracts the communication channel from communicating processors of the modules. A processor of each module interacts with the communication channel through the bus controller. In this manner, the communication channel is decoupled from the processor, allowing different processors running at different speeds to share the communication channel without impacting throughput of the communication channel. The bus controller and the processors of the modules can employ a handshake protocol to asynchronously communicate with each other. The bus controllers can employ a reconfigurable TDMA protocol to communicate with each other and/or communicate between modules.
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Citations
20 Claims
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1. A computer bus system, comprising:
a plurality of modules, each module comprising a processor and a bus controller that manages a communication channel coupling the plurality of modules, where the bus controller employs a reconfigurable protocol to asynchronously communicate with the processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A bus system, comprising:
a plurality of modules, each module including a processor and a programmable logic device for managing a parallel bus that interconnects the plurality of modules, where the programmable logic device and the processors employ a handshake protocol for asynchronous communications. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A computer-implemented method of writing a byte of data from a bus controller, comprising:
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waiting for an acknowledge signal to be deactivated; activating a write signal; providing data on a parallel bus; activating a strobe signal; deactivating the strobe signal in response to activation of the acknowledge signal; and
,deactivating the write signal. - View Dependent Claims (19, 20)
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Specification