Reconfigurable computer bus

• US 20080273475A1
• Filed: 05/03/2007
• Published: 11/06/2008
• Est. Priority Date: 05/03/2007
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Zhao, Feng, Priyantha, Nissanka Bodhi, Lymberopoulos, Dimitrios
• Application Number:
  US11/799,806
• Publication Number:
  US 20080273475A1
• Time in Patent Office: Days
• US Class Current: 370/257
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A bus system in which a bus controller, such as a complex programmable logic device, manages a communication channel coupling modules which can implement a node in a sensor network and/or an embedded system device. The system abstracts the communication channel from communicating processors of the modules. A processor of each module interacts with the communication channel through the bus controller. In this manner, the communication channel is decoupled from the processor, allowing different processors running at different speeds to share the communication channel without impacting throughput of the communication channel. The bus controller and the processors of the modules can employ a handshake protocol to asynchronously communicate with each other. The bus controllers can employ a reconfigurable TDMA protocol to communicate with each other and/or communicate between modules.

Claims

1. A computer bus system, comprising:

a plurality of modules, each module comprising a processor and a bus controller that manages a communication channel coupling the plurality of modules, where the bus controller employs a reconfigurable protocol to asynchronously communicate with the processors.

2. The system of claim 1, wherein the protocol is a time division multiple access protocol.

3. The system of claim 1, wherein the bus controller is at least one of a complex programmable logic device or an application-specific integrated circuit.

4. The system of claim 1, wherein the communication channel is a parallel bus at least twenty four bits wide.

5. The system of claim 1, further comprising an asynchronous interface bus coupling the bus controller and the modules.

6. The system of claim 5, wherein the asynchronous interface bus is based on handshake signals.

7. The system of claim 1 employed in a sensor network to communicate with sensors.

8. The system of claim 1 employed as an embedded device platform.

9. The system of claim 1, wherein at least one processor operates at speed that is different than another processor.

10. The system of claim 1, wherein the bus controller allows processors of the modules to operate at different speeds while sharing the communication channel.

11. A bus system, comprising:

a plurality of modules, each module including a processor and a programmable logic device for managing a parallel bus that interconnects the plurality of modules, where the programmable logic device and the processors employ a handshake protocol for asynchronous communications.

12. The system of claim 11, further comprising an asynchronous interface bus for interconnecting the programmable logic device and the processors.

13. The system of claim 12, wherein the asynchronous interface bus is an eight bit parallel bus.

14. The system of claim 11, wherein the parallel bus employs a time division multiple access protocol to share the parallel bus across a multiple of bus controllers.

15. The system of claim 11, further comprising a configuration bus for configuring the programmable logic device and the modules.

16. The system of claim 11, the programmable logic device further comprised a processor interface for transferring packets from the processors for communication across the parallel bus.

17. The system of claim 11, further comprising signal lines that facilitate asynchronous communication between the processor and the programmable logic device.

18. A computer-implemented method of writing a byte of data from a bus controller, comprising:

waiting for an acknowledge signal to be deactivated;

activating a write signal;

providing data on a parallel bus;

activating a strobe signal;

deactivating the strobe signal in response to activation of the acknowledge signal; and

,

deactivating the write signal.

19. The method of claim 18 employed to transfer data from a processor to the bus controller in a sensor network.

20. The method of claim 18, further comprising:

acquiring data on the parallel bus by the bus controller;

activating the acknowledge signal by the bus controller; and

,

deactivating the acknowledge signal in response to deactivation of the write signal.