Wafer level device package with sealing line having electroconductive pattern and method of packaging the same
First Claim
1. A wafer level package comprising:
- a device substrate comprising a device region, where a device is mounted, on the top surface;
a sealing line comprising a plurality of non-electroconductive patterns and a plurality of electroconductive patterns and sealing the device region; and
a cap substrate comprising a plurality of vias respectively connected to the electroconductive patterns and being attached to the device substrate by the sealing line.
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Accused Products
Abstract
Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.
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Citations
15 Claims
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1. A wafer level package comprising:
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a device substrate comprising a device region, where a device is mounted, on the top surface; a sealing line comprising a plurality of non-electroconductive patterns and a plurality of electroconductive patterns and sealing the device region; and a cap substrate comprising a plurality of vias respectively connected to the electroconductive patterns and being attached to the device substrate by the sealing line. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of packaging a wafer level device, the method comprising:
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forming a device and a plurality of connecting patterns electrically connected to the device on a top surface of a first wafer for a device substrate; forming a sealing line that comprises a plurality of electroconductive patterns connected to the connecting patterns and a plurality of non-electroconductive patterns and surrounds the device region; attaching a second wafer for a cap substrate to the first wafer by the sealing line; forming a plurality of vias respectively connected to the electroconductive patterns of the sealing line in the second wafer; and a performing a dicing process along the sealing line so as to separate wafer level packages sealing the device. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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Specification