Wafer level device package with sealing line having electroconductive pattern and method of packaging the same

• US 20080290479A1
• Filed: 05/22/2008
• Published: 11/27/2008
• Est. Priority Date: 05/22/2007
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Hong, Ju Pyo, Kim, Tae Hoon, Park, Seung Wook, Ha, Job, Choi, Seog Moon
• Granted Patent: US 7,911,043 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: B81B 2207/093 Conductive package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H03H 9/1057 for microelectro-mechanical devices
• CPC Class Codes: H03H 9/1071 the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device

Abstract

Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

Claims

1. A wafer level package comprising:

a device substrate comprising a device region, where a device is mounted, on the top surface;

a sealing line comprising a plurality of non-electroconductive patterns and a plurality of electroconductive patterns and sealing the device region; and

a cap substrate comprising a plurality of vias respectively connected to the electroconductive patterns and being attached to the device substrate by the sealing line.

2. The wafer level package of claim 1, wherein a plurality of lead frames are disposed on the top surface of the device substrate and connected between the device and the electroconductive patterns of the sealing line.

3. The wafer level package of claim 1, wherein the electroconductive patterns have a larger area than the non-electroconductive patterns of the sealing line.

4. The wafer level package of claim 3, wherein each of the vias penetrates the cap substrate to be connected to one portion of each of the electroconductive patterns.

5. The wafer level package of claim 1, wherein the non-electroconductive patterns are formed of one selected from benzocyclobutene (BCB), dry film resin (DFR), epoxy, and thermosetting polymer.

6. The wafer level package of claim 1, wherein the electroconductive patterns are formed of metal or electroconductive paste.

7. A method of packaging a wafer level device, the method comprising:

forming a device and a plurality of connecting patterns electrically connected to the device on a top surface of a first wafer for a device substrate;

forming a sealing line that comprises a plurality of electroconductive patterns connected to the connecting patterns and a plurality of non-electroconductive patterns and surrounds the device region;

attaching a second wafer for a cap substrate to the first wafer by the sealing line;

forming a plurality of vias respectively connected to the electroconductive patterns of the sealing line in the second wafer; and

a performing a dicing process along the sealing line so as to separate wafer level packages sealing the device.

8. The method of claim 7, wherein the connecting patterns comprises lead frames.

9. The method of claim 7, wherein, in the forming of the sealing line, the non-electroconductive patterns are formed of one selected from benzocyclobutene (BCB), dry film resin (DFR), epoxy, and thermosetting polymer using screen printing or injection through a nozzle.

10. The method of claim 7, wherein, in the forming of the sealing line, the electroconductive patterns are formed of electroconductive paste using screen printing or injection through a nozzle.

11. The method of claim 7, wherein, in the forming of the sealing line, the electroconductive patterns are formed of metal using physical vapor deposition (PVD).

12. The method of claim 7, wherein a scribe line that penetrates the plurality of vias along the sealing line is used in the performing of the dicing process.

13. The method of claim 7, wherein the forming of the vias comprises:

performing an etch process using a photoresist pattern that exposes a portion in contact with the electroconductive patterns so as to form via holes; and

filling the via holes with metal or electroconductive paste.

14. The method of claim 13, wherein, in the case of filling the via holes with the metal, the metal is filled using physical vapor deposition (PVD) and the via is planarized using a chemical mechanical polishing (CMP) process.

15. The method of claim 13, wherein, in the case of filling the via holes with the electroconductive paste, the electroconductive paste is filled using screen printing.