METHOD FOR FORMING POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS
First Claim
1. A method of forming a bipolar transistor comprising the steps of:
- (a) depositing a layer of amorphous semiconductor material comprising silicon, germanium or silicon-germanium above a substrate;
(b) depositing a metal in contact with the amorphous semiconductor material; and
(c) annealing to react the metal with the amorphous semiconductor material to form a crystallization template layer comprising metal silicide, metal germanide or metal silicide-germanide and to crystallize the layer of semiconductor material.
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Accused Products
Abstract
A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.
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Citations
26 Claims
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1. A method of forming a bipolar transistor comprising the steps of:
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(a) depositing a layer of amorphous semiconductor material comprising silicon, germanium or silicon-germanium above a substrate; (b) depositing a metal in contact with the amorphous semiconductor material; and (c) annealing to react the metal with the amorphous semiconductor material to form a crystallization template layer comprising metal silicide, metal germanide or metal silicide-germanide and to crystallize the layer of semiconductor material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for making a thin film bipolar transistor comprising the steps of:
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(a) depositing a layer of amorphous silicon above a substrate; (b) doping a first portion and a second portion of the amorphous silicon layer with a p-type or n-type dopant; (c) depositing a layer of silicide-forming metal adjacent to the amorphous silicon layer; and (d) thermally annealing to react the metal and the silicon to form a metal silicide and to crystallize the amorphous silicon to polysilicon, wherein the bipolar transistor has a collector region and an emitter region corresponding to the p-type or n-type doped first and second portions of the silicon layer and a base region formed in the silicon layer. - View Dependent Claims (17, 18, 19)
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20. A method for forming a memory select device comprising the steps of:
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(a) monolithically forming a first memory level of first memory cells above a substrate, each first memory cell comprising a vertically oriented p-i-n diode, the cells being arranged in rows and columns within the first memory level; and (b) forming one or more first bipolar transistor in operative connection to and substantially coplanar with the first memory cells, wherein the first memory cells and the first bipolar transistors comprise deposited semiconductor material crystallized in contact with cobalt silicide or titanium silicide, wherein the first bipolar transistors are capable of selectively programming one or more of the first memory cells. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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Specification