METHOD FOR FORMING POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS

• US 20080311722A1
• Filed: 06/15/2007
• Published: 12/18/2008
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Petti, Christopher J., Herner, S. Brad
• Granted Patent: US 7,855,119 B2
• Time in Patent Office: Days
• US Class Current: 438/378
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 29/66265 Thin film bipolar transistors H01L29/66242 takes precedence
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors

Abstract

A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.

Claims

1. A method of forming a bipolar transistor comprising the steps of:

(a) depositing a layer of amorphous semiconductor material comprising silicon, germanium or silicon-germanium above a substrate;

(b) depositing a metal in contact with the amorphous semiconductor material; and

(c) annealing to react the metal with the amorphous semiconductor material to form a crystallization template layer comprising metal silicide, metal germanide or metal silicide-germanide and to crystallize the layer of semiconductor material.

2. The method of claim 1 wherein the bipolar transistor comprises a base region, a collector region and an emitter region formed in the crystallized semiconductor material.

3. The method of claim 2 further comprising the step of doping the emitter and collector regions with a p-type dopant to form a p-n-p bipolar transistor.

4. The method of claim 1 wherein the metal comprises titanium or cobalt.

5. The method of claim 4 wherein the metal comprises titanium.

6. The method of claim 5 wherein the semiconductor material comprises silicon.

7. The method of claim 5 wherein the semiconductor material comprises germanium.

8. The method of claim 5 wherein the semiconductor material comprises silicon-germanium.

9. The method of claim 1 wherein the annealing step is done by a rapid thermal anneal.

10. The method of claim 2 wherein the bipolar transistor is operatively connected to a first plurality of memory cells formed above the substrate.

11. The method of claim 10 wherein each of the first plurality of memory cells comprises the crystallized semiconductor material.

12. The method of claim 10 wherein the bipolar transistor is operatively connected to control circuitry disposed in the substrate.

13. The method of claim 12 wherein the bipolar transistor is capable of selectively programming one or more of the first memory cells.

14. The method of claim 13 further comprising the step of applying a programming voltage to the bipolar transistor to program one or more of the first memory cells.

15. The method of claim 1 wherein the substrate is a portion of a monocrystalline silicon wafer.

16. A method for making a thin film bipolar transistor comprising the steps of:

(a) depositing a layer of amorphous silicon above a substrate;

(b) doping a first portion and a second portion of the amorphous silicon layer with a p-type or n-type dopant;

(c) depositing a layer of silicide-forming metal adjacent to the amorphous silicon layer; and

(d) thermally annealing to react the metal and the silicon to form a metal silicide and to crystallize the amorphous silicon to polysilicon,

wherein the bipolar transistor has a collector region and an emitter region corresponding to the p-type or n-type doped first and second portions of the silicon layer and a base region formed in the silicon layer.

17. The method of claim 16 wherein the silicide-forming metal is titanium.

18. The method of claim 17 wherein the metal silicide is titanium silicide.

19. The method of claim 18 wherein the titanium silicide is predominantly C49 phase titanium silicide.

20. A method for forming a memory select device comprising the steps of:

(a) monolithically forming a first memory level of first memory cells above a substrate, each first memory cell comprising a vertically oriented p-i-n diode, the cells being arranged in rows and columns within the first memory level; and

(b) forming one or more first bipolar transistor in operative connection to and substantially coplanar with the first memory cells, wherein the first memory cells and the first bipolar transistors comprise deposited semiconductor material crystallized in contact with cobalt silicide or titanium silicide, wherein the first bipolar transistors are capable of selectively programming one or more of the first memory cells.

21. The method of claim 20 further comprising the step of monolithically forming a second memory level of second memory cells, the second memory level being formed above the first memory level.

22. The method of claim 21 further comprising the step of forming one or more second bipolar transistors in operative connection to and substantially coplanar with the second memory cells, wherein the second memory cells and the second bipolar transistors comprise deposited semiconductor material crystallized in contact with cobalt silicide or titanium silicide, and wherein the second bipolar transistors are capable of selectively programming one or more of the second memory cells.

23. The method of claim 20 wherein the substrate comprises a portion of a silicon wafer.

24. The method of claim 22 wherein the first and second memory cells and the first and second bipolar transistors comprise deposited semiconductor material crystallized in contact with titanium silicide.

25. The method of claim 24 wherein the titanium silicide is predominantly C49 phase titanium silidice.

26. The method of claim 22 further comprising the step of monolithically forming additional memory levels above the first memory level, with corresponding additional bipolar transistors being formed within respective memory levels in operative connection to and substantially coplanar with the memory cells of that level.