METHODS OF FABRICATING DUAL FIN STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FIN STRUCTURES

• US 20090032866A1
• Filed: 07/31/2007
• Published: 02/05/2009
• Est. Priority Date: 07/31/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: McDaniel, Terrence
• Granted Patent: US 7,902,057 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a plurality of trenches in a substrate with at least one protruding region therebetween;

applying a mask material overlying the dielectric material;

exposing a portion of an upper end of the at least one protruding region through the mask material to form a mask; and

forming a pair of fins from the at least one protruding region by removing the exposed portion of the substrate at the upper end of the at least one protruding region to form a trench therein.

2. The method of claim 1, wherein exposing the upper end of the at least one protruding region comprises rendering the mask material substantially coplanar with the upper end of the protruding region.

3. The method of claim 1, wherein exposing the upper end of the at least one protruding region comprises polishing the mask material.

4. The method of claim 1, wherein forming the plurality of trenches in the substrate comprises selectively removing at least a portion of a silicon substrate.

5. The method of claim 1, wherein forming the plurality of trenches in the substrate comprises forming the at least one protruding region with a height of about 100 Å

to about 10,000 Å

from bases of the trenches.

6. The method of claim 1, wherein applying the mask material comprises applying a dielectric material over the at least one protruding region.

7. The method of claim 1, wherein applying the mask material comprises applying a conductive material over the at least one protruding region.

8. The method of claim 7, wherein applying a conductive material comprises applying at least one of titanuim niritride, tungsten nitride, tungsten silicide, titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten, tantalum and tantalum nitride.

9. The method of claim 7, wherein applying the mask material further comprises applying a dielectric material over the at least one protruding region, and further comprising applying a conductive material over the dielectric material.

10. The method of claim 9, wherein applying the dielectric material comprises forming a gate dielectric over the pair of fins.

11. The method of claim 10, further comprising:

patterning the conductive material to define at least one conductive element of at least one transistor gate.

12. The method of claim 7, further comprising;

patterning the conductive material to define at least one conductive element.

13. A method for fabricating a semiconductor device, comprising:

forming a plurality of trenches in a substrate to form a plurality of protrusions therebetween;

applying a mask material over the substrate and over the plurality of protrusions;

exposing portions of upper ends of the plurality of protrusions by removing at least a portion of the mask material;

forming fin structures from the protrusions by removing substrate material from the exposed portions of the upper ends of the plurality protrusions and form recesses therein;

applying a dielectric material over the substrate to form a lining on the sidewalls of the recesses;

applying a conductive material over the plurality of protrusions to fill the recesses; and

forming conductive lines on the fin structures on sides thereof opposite the recesses.

14. The method of claim 13, wherein forming a plurality of trenches in a substrate with a plurality of protrusions therebetween comprises forming a plurality of trenches in a silicon substrate.

15. The method of claim 13, wherein forming a plurality of trenches in a substrate with a plurality of protrusions therebetween comprises forming a plurality of trenches with a depth of from about 100 Å

to about 10,000 Å

.

16. The method of claim 13, wherein applying a conductive material over the plurality of protrusions to fill the recesses comprises applying a conductive material selected from the group comprising titanuim niritride, tungsten nitride, tungsten silicide, titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten, tantalum and tantalum nitride.

17. The method of claim 13, wherein applying a conductive material over the plurality of protrusions comprises applying titanuim nitride (TiN).

18. The method of claim 13, wherein exposing portions of upper ends of the plurality of protrusions comprises removing at least a portion of the mask material to render the remaining mask material substantially coplanar with the upper ends of the plurality of protrusions.

19. The method of claim 13, wherein exposing portions of the upper ends of the protrusions comprises chemical-mechanical polishing at least a portion of the mask material to render the remaining mask material substantially coplanar with the upper ends of the plurality of protrusions.

20. The method of claim 13, wherein forming recesses within the plurality of protrusions by removing substrate material from the exposed portions of the upper ends thereof comprises forming a recesses extending below the bottoms of the plurality of trenches.

21. The method of claim 13, wherein forming recesses within the protrusions comprises forming recesses with bottoms substantially coplanar with bottoms of the plurality of trenches.

22. The method of claim 13, wherein removing a portion of the dielectric material to form a lining on the sidewalls of the recesses comprises etching the dielectric material.

23. The method of claim 13, wherein applying a conductive material to fill the recesses comprises applying a conductive material selected from the group comprising titanuim niritride, tungsten nitride, tungsten silicide, titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten, tantalum and tantalum nitride.

24. The method of claim 13, wherein forming conductive lines on the fin structures comprises removing at least a portion of the mask material to form the conductive lines on the sides of the fin structures.

25. The method of claim 13, wherein forming conductive lines on the fin structures comprises depositing a conductive material over the outer surfaces of the protrusions and removing portions thereof.

26. A semiconductor device structure, comprising:

at least one protruding region extending from a surface of a substrate comprising a semiconductor material;

a layer of mask material over the surface of the substrate and outer surfaces of the at least one protruding region; and

a recess extending centrally through the semiconductor material of at least a portion of the at least one protruding region.

27. The semiconductor device of claim 26, wherein the mask material comprises a conductive material.

28. The semiconductor device of claim 27, wherein the conductive material is selected from the group comprising titanuim nitride, tungsten nitride, tungsten silicide, titanium silicide, platinum silicide, cobalt silicide, nickel silicide, tungsten, tantalum and tantalum nitride.

29. The semiconductor device of claim 27, further comprising:

dielectric material between the conductive material and the outer surfaces of the at least one protruding region.

30. An electronic device, comprising:

at least one semiconductor device, including;

a substrate comprising semiconductor material;

at least one protruding region extending from an active surface of the substrate;

a layer of mask material over the active surface of the substrate and outer surfaces of the at least one protruding region; and

a recess extending centrally through the semiconductor material of at least a portion of the at least one protruding region.

31. The electronic device of claim 30, wherein the mask material comprises a conductive material.

32. The electronic device of claim 31, further comprising:

dielectric material between the conductive material and the outer surfaces of the at least one protruding region.

33. The electronic device of claim 32, wherein the dielectric material comprises a gate dielectric and the conductive material comprises at least one gate electrode.