METHODS AND SYSTEMS FOR COMPUTER AIDED DESIGN OF 3D INTEGRATED CIRCUITS
First Claim
1. A method for defining a 3-D technology file structure, the method comprising the steps of:
- providing an identifier for each one of at least two circuit levels, constituting at least two circuit level identifiers;
providing for each one of said at least two circuit levels, an identifier for a 2-D technology file corresponding to said one of said at least two circuit levels;
said identifier for the 2-D technology file comprising a pointer to the 2-D technology file; and
providing a file structure comprisingsaid at least two circuit level identifiers;
said identifier, for said each one of said at least two circuit levels, for the 2-D technology file corresponding to said one of said at least two circuit levels;
providing, if a bond layer needs to be defined, an identifier for the bond layer disposed between said at least two circuit levels; and
providing a list comprising said at least two circuit level identifiers and said identifier for said bond layer, if the bond layer needs to be defined, said at least two circuit level identifiers and said identifier for a bond layer being located in an order in which said at least two circuit levels and said bond layer are located in a 3-D device.
1 Assignment
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Accused Products
Abstract
Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.
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Citations
32 Claims
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1. A method for defining a 3-D technology file structure, the method comprising the steps of:
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providing an identifier for each one of at least two circuit levels, constituting at least two circuit level identifiers; providing for each one of said at least two circuit levels, an identifier for a 2-D technology file corresponding to said one of said at least two circuit levels;
said identifier for the 2-D technology file comprising a pointer to the 2-D technology file; andproviding a file structure comprising said at least two circuit level identifiers; said identifier, for said each one of said at least two circuit levels, for the 2-D technology file corresponding to said one of said at least two circuit levels; providing, if a bond layer needs to be defined, an identifier for the bond layer disposed between said at least two circuit levels; and providing a list comprising said at least two circuit level identifiers and said identifier for said bond layer, if the bond layer needs to be defined, said at least two circuit level identifiers and said identifier for a bond layer being located in an order in which said at least two circuit levels and said bond layer are located in a 3-D device. - View Dependent Claims (6, 7, 8, 9)
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2. (canceled)
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3. (canceled)
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10. A system comprising:
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at least one processor; a computer usable medium for storing data for access by computer readable code being executed on said at least one processor, said computer usable medium comprising; a data structure stored in said computer readable medium, said data structure including; at least two data objects, each of said at least two data objects comprising an identifier for a distinct one of at least two circuit levels, and an identifier, for each one of said at least two circuit levels, identifying a 2-D technology file corresponding to said one of said at least two circuit levels;
said identifier comprising a pointer to the 2-D technology file;an identifier, if a bond layer needs to be defined, for the bond layer disposed between said at least two circuit levels, and a list comprising said at least two circuit level identifiers and said identifier for said bond layer if the bond layer needs to be defined, said at least two circuit level identifiers and said identifier for a bond layer being located in an order in which said at least two circuit levels and said bond layer are located in a 3-D device; another computer usable medium having computer readable code embodied therein, said computer readable code capable of causing said at least one processor to; input said data structure, and input each 2-D technology file corresponding to said each one of said at least two circuit levels; wherein said each 2-D technology file is inputted only once. - View Dependent Claims (11)
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12. A computer usable medium for storing data for access by computer readable code being executed on said at least one processor, said computer usable medium comprising:
a data structure stored in said computer readable medium, said data structure comprising; a root data structure comprising; a root node data object stored in said computer usable medium, said root node data object identifying a 3-D structure, and a plurality of branch reference data objects; a plurality of branch data structures, each branch data structure from said plurality of branch data structures comprising; a data object stored in said computer usable medium, said data object identifying one distinct circuit level from a plurality of circuit levels, and a reference data object corresponding to said data object, said corresponding reference data object providing a pointer to a data structure comprising a list of geometric shapes corresponding to said one distinct circuit level; and each one branch reference data object from said plurality of branch reference data objects providing a pointer to one branch data structure from said plurality of branch data structures; said plurality of circuit levels including at least one 3-D design layer; and a plurality of other data objects stored in said computer usable medium, each other data object of said plurality of other data objects identifying a child cell; and
another corresponding reference data object for each one other data object from said plurality of other data objects, said another corresponding reference data object providing a pointer to one branch data structure from said plurality of branch data structures, said one branch data structure identifying a circuit level, said child cell identified by said one other data object being assigned to said circuit level identified by said one branch data structure;whereby a 3-D design can be referenced as a 3-D structure or as circuit level projections. - View Dependent Claims (14)
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13. (canceled)
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15. A method for defining a data structure, the method comprising the steps of:
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providing a plurality of data objects stored in a computer usable medium, each data object from said plurality of data objects identifying one circuit level from a plurality of circuit levels; and providing a corresponding reference data object for each data object from said plurality of data objects, said corresponding reference data object providing a pointer to a data structure comprising a list of geometric shapes; wherein said plurality of circuit levels includes at least one 3-D design layer; providing another plurality of other data objects stored in said computer usable medium each other data object of said another plurality of other data objects identifying a child cell; providing another corresponding reference data object for each one other data object from said another plurality of other data objects, said another corresponding reference data object providing a pointer to one data object from said plurality of data objects, said pointer pointing to said one data object identifying a circuit level, said child cell identified by said one other data object being assigned to said circuit level identified by said one data object; and providing a circuit level projection of a 3-D child cell onto a selected circuit level; providing one other data object of said another plurality of other data, said one other data object identifying said circuit level projection of a 3-D child cell; and providing another corresponding reference data object for said one other data object from said another plurality of other data objects, said another corresponding reference data object providing a pointer to said one data object from said plurality of data objects, said pointer pointing to said one data object identifying said selected circuit level; whereby a 3-D design can be referenced as a 3-D structure or as circuit level projections. - View Dependent Claims (17, 18, 19)
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16. (canceled)
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20. (canceled)
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21. A method for layout for a 3-D integrated circuit, the method comprising the steps of:
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identifying a dimensionality of a cell; and selecting a circuit level for a 3-D cell. - View Dependent Claims (22, 23, 24, 25)
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26. A user interface comprising:
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a component capable of enabling input of a cell name for a cell; and a component capable of selecting a technology for said cell. - View Dependent Claims (27)
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28. A user interface for providing information for a layout of a 3-D integrated circuit, the user interface comprising:
a component capable of selecting a circuit level for a 3-D cell. - View Dependent Claims (29)
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30. A user interface comprising:
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a component capable of enabling input of a cell name for a child cell; and a component capable of selecting a circuit level for said child cell. - View Dependent Claims (31)
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32. A system for layout for a 3-D integrated circuit, the system comprising:
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at least one processor; a display device; at least one computer usable medium having computer readable code embodied there in, said computer readable code being capable of causing said at least one processor to; provide a user interface comprising; a component capable of enabling input of a cell name for a cell; and a component capable of selecting a technology for said cell; a component capable of selecting a circuit level for a 3-D cell; and a component capable of enabling input of a cell name for a child cell; and a component capable of selecting a circuit level for said child cell.
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Specification