Methods and systems for computer aided design of 3D integrated circuits

• US 7,526,739 B2
• Filed: 07/13/2006
• Issued: 04/28/2009
• Est. Priority Date: 07/26/2005
• Status: Expired due to Fees

• Current Assignee: R3 Logic, Inc.
• Original Assignee: R3 Logic, Inc.
• Inventors: McIlrath, Lisa G.
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Doan, Nghia M
• Application Number:
  US11/485,883
• Publication Number:
  US 20090064058A1
• Time in Patent Office: 1,020 Days
• Field of Search: 716 1- 21, 703 13- 22
• US Class Current: 716/118
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Claims

1. A method for defining a 3-D technology file structure, the method comprising the steps of:

providing an identifier for each one of at least two circuit levels, constituting at least two circuit level identifiers;

providing for each one of said at least two circuit levels, an identifier for a 2-D technology file corresponding to said one of said at least two circuit levels;

said identifier for the 2-D technology file comprising a pointer to the 2-D technology file; and

providing a file structure comprising

said at least two circuit level identifiers;

said identifier, for said each one of said at least two circuit levels, for the 2-D technology file corresponding to said one of said at least two circuit levels;

providing, an identifier for the bond layer disposed between said at least two circuit levels; and

providing a list comprising said at least two circuit level identifiers and said identifier for said bond layer said at least two circuit level identifiers and said identifier for a bond layer being located in an order in which said at least two circuit levels and said bond layer are located in a 3-D device;

the 3-D technology file structure being stored in a computer usable medium and being accessible by executing computer readable code on at least one processor;

whereby the 3-D technology file structure is utilized in generating and verifying circuit layout for 3-D integrated circuits.

2. The method of claim 1 further comprising the steps of:

providing at least one indicator of whether at least one of said at least two circuit levels is inverted when located in the 3-D device.

3. The method of claim 1 further comprising the step of:

providing design layer identifying information for layers formed in 3-D assembly of a 3-D device.

4. The method of claim 1 further comprising the step of:

providing rules for 3-D assembly.

5. The method of claim 1 further comprising the step of:

providing physical design rules for 3-D device integration.

6. The method of claim 1 further comprising the step of:

providing rules for generating physical masks for 3-D device fabrication.

7. A system comprising:

at least one processor;

a computer usable medium for storing data for access by computer readable code being executed on said at least one processor, said computer usable medium comprising;

a data structure stored in said computer readable medium, said data structure including;

at least two data objects, each of said at least two data objects comprising an identifier for a distinct one of at least two circuit levels, and

an identifier, for each one of said at least two circuit levels, identifying a 2-D technology file corresponding to said one of said at least two circuit levels;

said identifier comprising a pointer to the 2-D technology file;

an identifier for the bond layer disposed between said at least two circuit levels; and

a list comprising said at least two circuit level identifiers and said identifier for said bond layer, said at least two circuit level identifiers and said identifier for a bond layer being located in an order in which said at least two circuit levels and said bond layer are located in a 3-D device;

another computer usable medium having computer readable code embodied therein, said computer readable code capable of causing said at least one processor to;

input said data structure, and

input each 2-D technology file corresponding to said each one of said at least two circuit levels;

wherein said each 2-D technology file is inputted only once.

8. The system of claim 7 wherein said another computer usable medium is a same computer usable medium as said computer usable medium.

9. A computer usable medium for storing data for access by computer readable code being executed on said at least one processor, said computer usable medium comprising:

a data structure stored in said computer readable medium, said data structure comprising;

a root data structure comprising;

a root node data object stored in said computer usable medium, said root node data object identifying a 3-D structure, and

a plurality of branch reference data objects;

a plurality of branch data structures, each branch data structure from said plurality of branch data structures comprising;

a data object stored in said computer usable medium, said data object identifying one distinct circuit level from a plurality of circuit levels, and

a reference data object corresponding to said data object, said corresponding reference data object providing a pointer to a data structure comprising a list of geometric shapes corresponding to said one distinct circuit level; and

each one branch reference data object from said plurality of branch reference data objects providing a pointer to one branch data structure from said plurality of branch data structures;

said plurality of circuit levels including at least one 3-D design layer; and

a plurality of other data objects stored in said computer usable medium, each other data object of said plurality of other data objects identifying a child cell; and

another corresponding reference data object for each one other data object from said plurality of other data objects, said another corresponding reference data object providing a pointer to one branch data structure from said plurality of branch data structures, said one branch data structure identifying a circuit level, said child cell identified by said one other data object being assigned to said circuit level identified by said one branch data structure;

whereby a 3-D design can be referenced as a 3-D structure or as circuit level projections; and

whereby the data structure is utilized in generating and verifying circuit layout for 3-D integrated circuits.

10. The computer usable medium of claim 9 wherein said each branch data structure further comprises:

another corresponding reference data object, said another corresponding reference data object providing a pointer to a data structure comprising a list of child cells.

11. A method for defining a data structure, the method comprising the steps of:

providing a plurality of data objects stored in a computer usable medium, each data object from said plurality of data objects identifying one circuit level from a plurality of circuit levels; and

providing a corresponding reference data object for each data object from said plurality of data objects, said corresponding reference data object providing a pointer to a data structure comprising a list of geometric shapes;

wherein said plurality of circuit levels includes at least one 3-D design layer;

providing another plurality of other data objects stored in said computer usable medium, each other data object of said another plurality of other data objects identifying a child cell;

providing another corresponding reference data object for each one other data object from said another plurality of other data objects, said another corresponding reference data object providing a pointer to one data object from said plurality of data objects, said pointer pointing to said one data object identifying a circuit level, said child cell identified by said one other data object being assigned to said circuit level identified by said one data object; and

providing a circuit level projection of a 3-D child cell onto a selected circuit level;

providing one other data object of said another plurality of other data, said one other data object identifying said circuit level projection of a 3-D child cell; and

providing another corresponding reference data object for said one other data object from said another plurality of other data objects, said another corresponding reference data object providing a pointer to said one data object from said plurality of data objects, said pointer pointing to said one data object identifying said selected circuit level;

the data structure being stored in a computer usable medium and being accessible by executing computer readable code on at least one processor;

whereby a 3-D design can be referenced as a 3-D structure or as circuit level projections whereby the data structure is utilized in generating and verifying circuit layout for 3-D integrated circuits.

12. The method of claim 11 wherein a single data object from said plurality of data objects is provided for 3-D material layers.

13. The method of claim 11 further comprising the steps of:

providing another corresponding reference data object for each data object from said plurality of data objects, said corresponding reference data object providing a pointer to a data structure comprising a list of child cells;

wherein one list of child cells is a list of 3-D child cells.

14. The method of claim 13 further comprising the steps of:

providing a circuit level projection of a 3-D child cell onto a circuit level; and

including an identifier for said circuit level projection in the list of child cells which is referenced by said another corresponding reference data object for the data object identifying said circuit level.