DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME

• US 20090106484A1
• Filed: 02/04/2008
• Published: 04/23/2009
• Est. Priority Date: 10/19/2007
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Yeh, Chih-Kang, Chu, Chien-Hua, Fu, Jia-Yi
• Granted Patent: US 8,001,317 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.

Claims

1. A data writing method for a non-volatile memory, comprising:

respectively using a plurality of blocks in a substitution area of the non-volatile memory for substituting a plurality of blocks in a data area of the non-volatile memory, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from a spare area of the non-volatile memory; and

using a plurality of temporary blocks of the non-volatile memory as a temporary area of the blocks in the substitution area,

wherein the temporary area is used for temporarily storing data to be written into the blocks in the substitution area.

2. The data writing method according to claim 1, wherein the non-volatile memory comprises replacement area, and at least one of the temporary blocks is selected from the replacement area.

3. The data writing method according to claim 1, wherein when the blocks in the substitution area are attached right after where data is previously recorded for recording continuous write-back data, the related data is written into the temporary area.

4. The data writing method according to claim 1 further comprising using a temporary table for indicating valid data and invalid data in the temporary area and a mapping relationship between pages in the temporary area and pages in the blocks in the substitution area.

5. The data writing method according to claim 1, wherein if the flash memory is a MLC NAND flash memory, only lower pages in the temporary blocks are used for writing data into the temporary area, wherein the write speed of the lower pages is faster than the write speed of upper pages in the temporary blocks.

6. The data writing method according to claim 1, wherein if the flash memory is a MLC NAND flash memory, only the pages having the fastest write speed or highest reliability in the temporary blocks are used for writing data into the temporary area.

16. The controller according to claim 1, wherein when the blocks in the substitution area are attached right after where data is previously recorded for recording continuous write-back data, the related data is written into the temporary area.

7. A data writing method for a non-volatile memory, wherein the non-volatile memory is a MLC NAND flash memory, and each block in the non-volatile memory comprises upper pages and lower pages, the data writing method comprising:

using only the lower pages for writing data in a part of the blocks,

wherein the write speed of the lower pages is faster than the write speed of the upper pages.

8. The data writing method according to claim 7 further comprising using only the lower pages of each block for writing the data.

9. The data writing method according to claim 7, wherein the data comprises at least one of a logical-physical mapping table, a cache file, a file allocation table (FAT), a firmware code, a defect block table (DBT) for recording defective blocks, a replace unit table (RUT) for managing defective block replacement, an info block for storing firmware parameters, and a variable table (VT) for storing variables.

10. The data writing method according to claim 7 further comprising establishing a page query table for recording the physical addresses of the lower pages.

11. The data writing method according to claim 7 further comprising establishing a logic conversion formula for calculating the physical addresses of the lower pages.

12. The data writing method according to claim 7, wherein the part of the blocks is a plurality of temporary blocks, and the temporary blocks are used as a temporary area of a plurality of blocks in a substitution area.

13. A controller, comprising:

a microprocessor unit, for controlling the operation of the controller;

a non-volatile memory interface, electrically connected to the microprocessor unit and used for accessing the non-volatile memory;

a buffer memory, electrically connected to the microprocessor unit and used for temporarily storing data; and

a memory management module, electrically connected to the microprocessor unit and used for managing the non-volatile memory,

wherein the memory management module respectively uses a plurality of blocks in a substitution area of the non-volatile memory for substituting a plurality of blocks in a data area of the non-volatile memory, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from a spare area of the non-volatile memory, and

wherein the memory management module uses a plurality of temporary blocks of the non-volatile memory as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing data to be written into the blocks in the substitution area.

14. The controller according to claim 13, wherein the non-volatile memory comprises a replacement area, and at least one of the temporary blocks is selected from the replacement area.

15. The controller according to claim 14, wherein the memory management module uses a temporary table for indicating valid data and invalid data in the temporary area and a mapping relationship between pages in the temporary area and pages in the blocks in the substitution area.

17. The controller according to claim 13, wherein the non-volatile memory is a SLC NAND flash memory or a MLC NAND flash memory.

18. The controller according to claim 17, wherein if the flash memory is the MLC NAND flash memory, the memory management module only uses lower pages in the temporary blocks for writing data into the temporary area, wherein the write speed of the lower pages is faster than the write speed of upper pages in the temporary blocks.

19. A controller, suitable for a storage device, wherein a non-volatile memory of the storage device is a MLC NAND flash memory, and each block in the non-volatile memory comprises upper pages and lower pages, the controller comprising:

a microprocessor unit, for controlling the operation of the controller;

a non-volatile memory interface, electrically connected to the microprocessor unit and used for accessing the non-volatile memory;

a buffer memory, electrically connected to the microprocessor unit and used for temporarily storing data; and

a memory management module, electrically connected to the microprocessor unit and used for managing the non-volatile memory,

wherein the memory management module only uses the lower pages for writing data in a part of the blocks,

wherein the write speed of the lower pages is faster than the write speed of the upper pages.

20. The controller according to claim 19, wherein the memory management module uses only the lower pages in each block for writing the data.

21. The controller according to claim 19, wherein the data comprises at least one of a logical-physical mapping table, a cache file, a FAT, a firmware code, a DBT for recording defective blocks, a RUT for managing defective block replacement, an info block for storing firmware parameters, and a VT for storing variables.

22. The controller according to claim 20, wherein the memory management module establishes a page query table for recording the physical addresses of the lower pages.

23. The controller according to claim 20, wherein the memory management module establishes a logic conversion formula for calculating the physical addresses of the lower pages.

24. The controller according to claim 20, wherein the part of the blocks is a plurality of temporary blocks, and the temporary blocks are used as a temporary area of a plurality of blocks in a substitution area.

25. A controller, suitable for a storage device, wherein a non-volatile memory of the storage device is a MLC NAND flash memory, and each block in the non-volatile memory comprises pages having at least two different write speeds, the controller comprising:

a microprocessor unit, for controlling the operation of the controller;

a non-volatile memory interface, electrically connected to the microprocessor unit and used for accessing the non-volatile memory;

a buffer memory, electrically connected to the microprocessor unit and used for temporarily storing data; and

a memory management module, electrically connected to the microprocessor unit and used for managing the non-volatile memory,

wherein the memory management module uses only the pages having the fastest write speed for writing data in at least one of the blocks.