PROCESSOR AND MEMORY CONTROL METHOD

• US 20090119456A1
• Filed: 03/14/2008
• Published: 05/07/2009
• Est. Priority Date: 11/06/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group), Seoul National University R&DB Foundation (Seoul National University)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group), Seoul National University R&DB Foundation (Seoul National University)
• Inventors: Suh, Dong Kwan, Jang, Choon Ki, Yoo, Dong-Hoon, Ryu, Soojung, Kim, Jeongwook, PARK, Il Hyun
• Granted Patent: US 9,015,451 B2
• Time in Patent Office: Days
• US Class Current: 711/125
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.

Claims

1. A processor comprising:

a processor core;

a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core; and

a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.

2. The processor of claim 1, wherein at least one of a load instruction and a store instruction executed in the processor core is allocated to any one of the cache and the SPM.

3. The processor of claim 2, wherein, when which memory of the cache and the SPM the at least one of the load instruction and the store instruction executed in the processor core is allocated to is undetermined while compiling, the at least one of the load instruction and the store instruction executed in the processor core is allocated to the cache.

4. The processor of claim 2, wherein a latency value is determined based on which of the cache and the SPM each of the load instruction and the store instruction executed in the processor core is allocated to, and each of the allocated load instruction and the allocated store instruction is scheduled based on the determined latency value.

5. The processor of claim 2, wherein the SPM assigns a time stamp value to each of the load instruction and the store instruction allocated to the SPM, and reduces, by one, the time stamp value for each clock cycle.

6. The processor of claim 2, wherein the cache selects any one of the load instruction and the store instruction to be forwarded to the SPM based on an address indicated by each of the load instruction and the store instruction allocated to the cache,

assigns a time stamp value to each of the selected load instruction and the selected store instruction, and

forwards, to the SPM, each of the load instruction and the store instruction to which the time stamp value is assigned.

7. The processor of claim 1, wherein a latency of the cache is less than a latency of the SPM.

8. The processor of claim 1, wherein the SPM comprises:

an input queue memory which stores, using a First In First Output (FIFO) scheme, at least one of a load instruction and a store instruction requested by the processor core; and

an output buffer which outputs a processing result of each of the load instruction and the store instruction processed by the SPM based on a latency of each of the processed load instruction and the processed store instruction.

9. The processor of claim 8, wherein the output buffer outputs the processing result according to a sequence in which a time stamp value of each of the processed load instruction and the processed store instruction is 0.

10. The processor of claim 8, wherein, when a time stamp value of each of the requested load instruction and the requested store instruction is predicted to be 0 while processing each of the requested load instruction and the requested store instruction, the SPM transmits a stall order to the processor core.

11. A memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:

analyzing a characteristic of at least one of a load instruction and a store instruction executed in the processor core;

allocating the at least one of the load instruction and the store instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic; and

processing the at least one of the allocated load instruction and the allocated store instruction.

12. The method of claim 11, wherein the processing comprises:

assigning a time stamp value to the at least one of the allocated load instruction and the allocated store instruction when the at least one of the load instruction and the store instruction is allocated to the multi-port SPM;

reducing, by one, the time stamp value for each clock cycle; and

outputting a processing result of the at least one of the load instruction and the store instruction when the time stamp value is 0.

13. The method of claim 11, wherein the processing comprises:

selecting any one of the load instruction and the store instruction to be forwarded to the multi-port SPM based on an address corresponding to the at least one of the allocated load instruction and the allocated store instruction; and

assigning a time stamp value to either the selected load instruction or the selected store instruction.

14. The method of claim 13, wherein the selecting comprises:

setting a start address and an end address of the single port cache; and

determining whether to forward, to the multi-port SPM, the at least one of the allocated load instruction and the allocated store instruction by comparing the address corresponding to the at least one of the allocated load instruction and the allocated store instruction with the start address and the end address.

15. The method of claim 11, wherein the multi-port SPM includes an output buffer and an input queue memory of an FIFO scheme, and the processing comprises:

storing, in the input queue memory, the at least one of the allocated load instruction and the allocated store instruction according to a scheduling-determined sequence;

processing the at least one of the load instruction and the store instruction being first stored in the input queue memory;

storing, in the output buffer, a processing result value of the at least one of the processed load instruction and the processed store instruction; and

outputting the processing result value stored in the output buffer when a time stamp value of the at least one of the processed load instruction and the processed store instruction is 0.

16. The method of claim 15, wherein the processing of the at least one of the allocated load instruction and the allocated store instruction further comprises:

transmitting a stall order to the processor core when a time stamp value of the at least one of the first-stored load instruction and the first-stored store instruction is predicted to be 0 while an operation of processing the at least one of the load instruction and the store instruction being first stored in the input queue memory is performed.

17. The method of claim 11, wherein, when which memory of the cache and the SPM the at least one of the load instruction and the store instruction executed in the processor core is allocated to is undetermined while compiling, the allocating allocates the at least one of the load instruction and the store instruction to the cache.

18. A computer-readable recording medium storing a program for implementing a memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:

analyzing a characteristic of at least one of a load instruction and a store instruction executed in the processor core;

allocating the at least one of the load instruction and the store instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic; and

processing the at least one of the allocated load instruction and the allocated store instruction.