PROCESSOR AND MEMORY CONTROL METHOD
First Claim
Patent Images
1. A processor comprising:
- a processor core;
a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core; and
a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
2 Assignments
0 Petitions
Accused Products
Abstract
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
-
Citations
18 Claims
-
1. A processor comprising:
-
a processor core; a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core; and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:
-
analyzing a characteristic of at least one of a load instruction and a store instruction executed in the processor core; allocating the at least one of the load instruction and the store instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic; and processing the at least one of the allocated load instruction and the allocated store instruction. - View Dependent Claims (12, 13, 14, 15, 16, 17)
-
-
18. A computer-readable recording medium storing a program for implementing a memory control method of a processor including a processor core, a single port cache, and a multi-port SPM, the method comprising:
-
analyzing a characteristic of at least one of a load instruction and a store instruction executed in the processor core; allocating the at least one of the load instruction and the store instruction to any one of the single port cache and the multi-port SPM based on the analyzed characteristic; and processing the at least one of the allocated load instruction and the allocated store instruction.
-
Specification