Partial Block Data Programming And Reading Operations In A Non-Volatile Memory
First Claim
1. In a re-programmable non-volatile semiconductor memory system having an array of charge storage elements, the array being divided into a plurality of sub-arrays in which the charge storage elements within individual sub-arrays are programmable independently, wherein the sub-arrays are individually divided into a plurality of blocks of charge storage elements that are erasable together, a method of operating the memory system, comprising:
- utilizing at least first and second of the plurality of blocks logically linked together as a metablock, the logically linked first and second of the plurality of blocks being positioned in at least respective first and second of the plurality of sub-arrays, the plurality of blocks being individually divided into a given number of a plurality of pages of charge storage elements that are programmable together,programming a first group of a plurality of pages in at least the first and second blocks with original data, the pages of original data having logical addresses associated therewith,maintaining an updatable address data structure that links one or more physical addresses of the first group of pages with one or more of the logical addresses associated with the data stored therein,programming an updated version of some of the original data and logical addresses associated with the updated version of the original data into a second group of one or more pages less than said given number in at least one update block other than the first and second blocks, wherein the logical addresses associated with the updated version of the original data programmed into the second group of pages are the same as those associated with the corresponding original data programmed into the first group of pages, and further wherein programming the second group of pages additionally comprises programming the updated version of the original data in those of the second group of pages that have different offset positions within the update block than offset positions of the first group of pages within the first and second blocks that contain original data having the same logical addresses associated therewith, andupdating the address data structure for the logical addresses of the updated version of the original data to include the physical addresses of the second group of pages of the update block in which the updated version of the original data has been programmed.
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Abstract
Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.
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Citations
23 Claims
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1. In a re-programmable non-volatile semiconductor memory system having an array of charge storage elements, the array being divided into a plurality of sub-arrays in which the charge storage elements within individual sub-arrays are programmable independently, wherein the sub-arrays are individually divided into a plurality of blocks of charge storage elements that are erasable together, a method of operating the memory system, comprising:
- utilizing at least first and second of the plurality of blocks logically linked together as a metablock, the logically linked first and second of the plurality of blocks being positioned in at least respective first and second of the plurality of sub-arrays, the plurality of blocks being individually divided into a given number of a plurality of pages of charge storage elements that are programmable together,
programming a first group of a plurality of pages in at least the first and second blocks with original data, the pages of original data having logical addresses associated therewith, maintaining an updatable address data structure that links one or more physical addresses of the first group of pages with one or more of the logical addresses associated with the data stored therein, programming an updated version of some of the original data and logical addresses associated with the updated version of the original data into a second group of one or more pages less than said given number in at least one update block other than the first and second blocks, wherein the logical addresses associated with the updated version of the original data programmed into the second group of pages are the same as those associated with the corresponding original data programmed into the first group of pages, and further wherein programming the second group of pages additionally comprises programming the updated version of the original data in those of the second group of pages that have different offset positions within the update block than offset positions of the first group of pages within the first and second blocks that contain original data having the same logical addresses associated therewith, and updating the address data structure for the logical addresses of the updated version of the original data to include the physical addresses of the second group of pages of the update block in which the updated version of the original data has been programmed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- utilizing at least first and second of the plurality of blocks logically linked together as a metablock, the logically linked first and second of the plurality of blocks being positioned in at least respective first and second of the plurality of sub-arrays, the plurality of blocks being individually divided into a given number of a plurality of pages of charge storage elements that are programmable together,
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16. In a re-programmable non-volatile semiconductor memory system having a plurality of blocks of a minimum number of memory charge storage elements that are erasable together as a unit, the plurality of blocks individually being divided into a plurality of a given number of pages of memory storage elements that are individually programmable as a unit and which have specified offset positions within their respective blocks, a method of operating the memory system, comprising:
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programming original data into individual ones of a first plurality of pages in at least a first block, the original data having logical addresses associated therewith, thereafter programming, into individual ones of a second plurality of pages in a second block, an updated version of less than the given number of pages of the original data programmed into the first plurality of pages, the updated version of the original data having logical addresses associated therewith, wherein the logical addresses associated with the updated version of the original data are the same as the logical addresses associated with the original data, wherein programming the second plurality of pages additionally comprises programming the updated version of the original data in those of the second plurality of pages that have different offset positions within the second block than the offset positions of the first plurality of pages within said at least the first block that contain original data with the same associated logical addresses, maintaining updatable address information that links physical addresses of the first and second blocks storing original and updated data with the logical addresses associated with the stored data, wherein the address information includes physical addresses of multiple blocks for individual logical addresses of original data having updated versions thereof, thereafter reading data from the first and second plurality of pages by a process that includes accessing the updatable address information, and organizing pages of the read data by their associated logical addresses. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification