MULTIPLE VOLTAGE THRESHOLD TIMING ANALYSIS FOR A DIGITAL INTEGRATED CIRCUIT

• US 20090193373A1
• Filed: 01/29/2008
• Published: 07/30/2009
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Abbaspour, Soroush, Feldmann, Peter
• Granted Patent: US 8,020,129 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.

Claims

1. A method for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, comprising:

obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance;

obtaining a model of the interconnect circuit;

deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit; and

generating a voltage waveform from the derived sequence of crossing times, wherein the generated voltage waveform is represented by the derived sequence of crossing times and corresponding sequence of voltage thresholds and is indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.

2. The method according to claim 1, wherein the obtaining of characterization data comprises accessing a library containing a plurality of tables representing the at least one logic gate loaded by various pure capacitive loads and excited by voltage waveforms of varying slew rates.

3. The method according to claim 1, wherein the obtaining of the model of the interconnect circuit comprises obtaining a reduced ordered model that is represented in a pole/residue form.

4. The method according to claim 1, wherein the deriving of a sequence of crossing times comprises estimating a charge supplied by the at least one logic gate to the interconnect circuit at each of the successive voltage thresholds provided in the driving point voltage waveform.

5. The method according to claim 4, further comprising determining a dynamic capacitance at each of the successive voltage thresholds from the estimated charges.

6. The method according to claim 5, further comprising determining each crossing time as a function of the dynamic capacitance and voltage thresholds.

7. The method according to claim 1, further comprising using the generated voltage waveform to perform a timing analysis of the digital integrated circuit.

8. The method according to claim 7, further comprising determining the timing of an entire path of the digital integrated circuit.

9. A computer-readable medium storing computer instructions, which when executed, enables a computer system to perform a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the computer instructions comprising:

obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance;

obtaining a model of the interconnect circuit;

deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit; and

generating a voltage waveform from the derived sequence of crossing times, wherein the generated voltage waveform is represented by the derived sequence of crossing times and corresponding sequence of voltage thresholds and is indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.

10. The computer-readable medium according to claim 9, wherein the obtaining of characterization data comprises instructions for accessing a library containing a plurality of tables representing the at least one logic gate loaded by various pure capacitive loads and excited by voltage waveforms of varying slew rates.

11. The computer-readable medium according to claim 9, wherein the obtaining of the model of the interconnect circuit comprises instructions for obtaining a reduced ordered model of the interconnect that is represented in a pole/residue form.

12. The computer-readable medium according to claim 9, wherein the deriving of a sequence of crossing times comprises instructions for estimating a charge supplied by the at least one logic gate to the interconnect circuit at each of the successive voltage thresholds provided in the driving point voltage waveform.

13. The computer-readable medium according to claim 12, further comprising instructions for determining a dynamic capacitance at each of the successive voltage thresholds from the estimated charges.

14. The computer-readable medium according to claim 13, further comprising instructions for determining each crossing time as a function of the dynamic capacitance and voltage thresholds.

15. The computer-readable medium according to claim 9, further comprising instructions for using the generated voltage waveform to perform a timing analysis of the digital integrated circuit.

16. The computer-readable medium according to claim 15, further comprising instructions for determining the timing of an entire path of the digital integrated circuit.

17. A computer system for performing a multiple voltage threshold timing analysis, comprising:

at least one processing unit;

memory operably associated with the at least one processing unit; and

a multiple voltage threshold timing analysis tool storable in memory and executable by the at least one processing unit for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the tool comprising;

a characterization data retrieving component configured to obtain characterization data describing driving behavior of the at least one logic gate, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance;

an interconnect circuit model retrieving component configured to obtain a model of the interconnect circuit; and

a multiple voltage threshold timing analysis component configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit and generate a voltage waveform from the derived sequence of crossing times, wherein the generated voltage waveform is represented by the derived sequence of crossing times and corresponding sequence of voltage thresholds and is indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.

18. The system according to claim 17, wherein the characterization data retrieving component is configured to obtain the characterization data from a library containing a plurality of tables representing the at least one logic gate loaded by various pure capacitive loads and excited by voltage waveforms of varying slew rates.

19. The system according to claim 17, wherein the interconnect circuit model retrieving component is configured to obtain a reduced ordered model of the interconnect that is in a pole/residue form.

20. The system according to claim 17, wherein the multiple voltage threshold timing analysis component is configured to estimate a charge supplied by the at least one logic gate to the interconnect circuit at each of the successive voltage thresholds provided in the driving point voltage waveform.

21. The system according to claim 20, wherein the multiple voltage threshold timing analysis component is further configured to determine a dynamic capacitance at each of the successive voltage thresholds from the estimated charges.

22. The system according to claim 21, wherein the multiple voltage threshold timing analysis component is further configured to determine each crossing time as a function of the dynamic capacitance and voltage thresholds.

23. The system according to claim 17, wherein the multiple voltage threshold timing analysis component is further configured to use the generated voltage waveform to perform a timing analysis of the digital integrated circuit.

24. The system according to claim 23, wherein the multiple voltage threshold timing analysis component is further configured to determine the timing of an entire path within the digital integrated circuit.