MULTIPLE VOLTAGE THRESHOLD TIMING ANALYSIS FOR A DIGITAL INTEGRATED CIRCUIT
First Claim
1. A method for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, comprising:
- obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance;
obtaining a model of the interconnect circuit;
deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit; and
generating a voltage waveform from the derived sequence of crossing times, wherein the generated voltage waveform is represented by the derived sequence of crossing times and corresponding sequence of voltage thresholds and is indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.
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Abstract
An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
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Citations
24 Claims
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1. A method for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, comprising:
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obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance; obtaining a model of the interconnect circuit; deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit; and generating a voltage waveform from the derived sequence of crossing times, wherein the generated voltage waveform is represented by the derived sequence of crossing times and corresponding sequence of voltage thresholds and is indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer-readable medium storing computer instructions, which when executed, enables a computer system to perform a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the computer instructions comprising:
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obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance; obtaining a model of the interconnect circuit; deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit; and generating a voltage waveform from the derived sequence of crossing times, wherein the generated voltage waveform is represented by the derived sequence of crossing times and corresponding sequence of voltage thresholds and is indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A computer system for performing a multiple voltage threshold timing analysis, comprising:
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at least one processing unit; memory operably associated with the at least one processing unit; and a multiple voltage threshold timing analysis tool storable in memory and executable by the at least one processing unit for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the tool comprising; a characterization data retrieving component configured to obtain characterization data describing driving behavior of the at least one logic gate, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance; an interconnect circuit model retrieving component configured to obtain a model of the interconnect circuit; and a multiple voltage threshold timing analysis component configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit and generate a voltage waveform from the derived sequence of crossing times, wherein the generated voltage waveform is represented by the derived sequence of crossing times and corresponding sequence of voltage thresholds and is indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification