CACHE MANAGEMENT DURING ASYNCHRONOUS MEMORY MOVE OPERATIONS
First Claim
1. A data processing system comprising:
- a processor;
a memory coupled to the processor and including a plurality of physical locations with real addresses that are utilized for storing data;
at least one lower level cache that buffers data from memory for utilization during processor execution;
processing logic for completing an asynchronous memory move (AMM) operation, wherein;
the processor receives an AMM ST instruction and processes an effective address move of data from a first effective address to a second effective address; and
asynchronous memory mover logic then completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, while the processor continues processing subsequently received instructions.
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Abstract
A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.
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Citations
14 Claims
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1. A data processing system comprising:
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a processor; a memory coupled to the processor and including a plurality of physical locations with real addresses that are utilized for storing data; at least one lower level cache that buffers data from memory for utilization during processor execution; processing logic for completing an asynchronous memory move (AMM) operation, wherein;
the processor receives an AMM ST instruction and processes an effective address move of data from a first effective address to a second effective address; and
asynchronous memory mover logic then completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, while the processor continues processing subsequently received instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. In a data processing system having a processor, a memory subsystem including a memory and at least one lower level cache, a method comprising:
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completing a move of data in virtual address space, in response to receiving an AMM ST instruction, wherein the move includes a processor-level move of data from a first effective address to a second effective address, and completing an asynchronous memory move (AMM) operation generated by the AMM ST instruction, wherein the AMM operation completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address, while the processor continues processing subsequently received instructions; performing an update to the at least one lower level cache based on the completion of the physical move. - View Dependent Claims (9, 10, 11, 14)
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12. The method of Clan 8, wherein the performing an update comprises:
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evaluating a size of the data being moved relative to a size of the at least one lower level cache; and forwarding only a first subset of the data to the at least one lower level cache when the size of the data exceeds a threshold size which would overrun the lower level cache. - View Dependent Claims (13)
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Specification