Cache management during asynchronous memory move operations
First Claim
1. A data processing system comprising:
- a processor;
a memory coupled to the processor and including a plurality of physical locations with real addresses that are utilized for storing data;
a memory controller that manages memory access operations;
an asynchronous memory mover communicatively coupled to but separate from the processor and the memory controller and which performs a physical move of data during an asynchronous memory move (AMM) operation, which AMM operation is initiated by execution by the processor of an asynchronous memory move (AMM) Store (ST) instruction that causes the processor to perform an effective address move of data as part of a corresponding AMM operation;
at least one lower level cache that buffers data from memory for utilization during processor execution;
processing logic executing on the processor for initiating the AMM operation, the AMM operation comprising;
the processor receiving the AMM ST instruction, wherein the AMM ST instruction comprises a status/control field that includes an indication of a requested treatment of one or more lower level cache(s) on completion of the corresponding AMM operation;
performing an effective address move of data from a first effective address to a second effective address provided by the AMM ST instruction, wherein the effective address move of data comprises the processor allocating the second effective address to the data in place of the first effective address and the effective address move of data triggers the asynchronous memory mover to initiate a physical move of the data within the memory; and
asynchronous memory mover logic executing on the asynchronous memory mover, wherein the asynchronous memory mover logic, in response to being triggered by the processor performing the effective address move of data, performs the functions of;
receiving the real address and other parameters of the AMM ST instruction; and
completing the physical move of the data from a first memory location in the memory having a first real address to a second memory location in the memory having a second real address while the processor continues processing subsequently received instructions, wherein the physical move is coordinated by the asynchronous memory mover along a path that does not include the processor.
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Abstract
A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.
113 Citations
20 Claims
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1. A data processing system comprising:
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a processor; a memory coupled to the processor and including a plurality of physical locations with real addresses that are utilized for storing data; a memory controller that manages memory access operations; an asynchronous memory mover communicatively coupled to but separate from the processor and the memory controller and which performs a physical move of data during an asynchronous memory move (AMM) operation, which AMM operation is initiated by execution by the processor of an asynchronous memory move (AMM) Store (ST) instruction that causes the processor to perform an effective address move of data as part of a corresponding AMM operation; at least one lower level cache that buffers data from memory for utilization during processor execution; processing logic executing on the processor for initiating the AMM operation, the AMM operation comprising; the processor receiving the AMM ST instruction, wherein the AMM ST instruction comprises a status/control field that includes an indication of a requested treatment of one or more lower level cache(s) on completion of the corresponding AMM operation; performing an effective address move of data from a first effective address to a second effective address provided by the AMM ST instruction, wherein the effective address move of data comprises the processor allocating the second effective address to the data in place of the first effective address and the effective address move of data triggers the asynchronous memory mover to initiate a physical move of the data within the memory; and asynchronous memory mover logic executing on the asynchronous memory mover, wherein the asynchronous memory mover logic, in response to being triggered by the processor performing the effective address move of data, performs the functions of; receiving the real address and other parameters of the AMM ST instruction; and completing the physical move of the data from a first memory location in the memory having a first real address to a second memory location in the memory having a second real address while the processor continues processing subsequently received instructions, wherein the physical move is coordinated by the asynchronous memory mover along a path that does not include the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. In a data processing system having a processor, an asynchronous memory mover, a memory subsystem including a memory, a memory controller, and at least one lower level cache, a method comprising:
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completing, via the processor, a move of data in virtual address space, in response to receiving an asynchronous memory move (AMM) store (ST) instruction, wherein the move includes a processor-level allocation of a second effective address to the data in place of a first effective address, to represent an effective address move of the data in virtual address space, wherein execution, by the processor, of the effective address move of data in virtual address space triggers the asynchronous memory mover to initiate a physical move of the data within the memory; in response to the trigger caused by the processor execution of the effective address move of data in virtual address space, completing, via the asynchronous memory mover, an asynchronous memory move (AMM) operation generated by the AMM ST instruction, wherein the AMM operation completes a physical move of the data from a first memory location in the memory having a first real address to a second memory location in the second memory having a second real address, while the processor continues processing subsequently received instructions, wherein the physical move is coordinated by the asynchronous memory mover along a path that does not include the processor; and performing an update to the at least one lower level cache based on the completion of the physical move and an included indication, within a status/control field of the AMM ST instruction, of a requested treatment of one or more lower level cache(s) on completion of the AMM operation; wherein the asynchronous memory mover is communicatively coupled to but separate from the processor and the memory controller; and wherein the asynchronous memory mover performs the physical move of data responsive to receipt of real addresses and other parameters associated with the AMM ST instruction. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification