MEMORY SYSTEM

• US 20090235015A1
• Filed: 03/10/2009
• Published: 09/17/2009
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takashima, Daisaburo, Hatsuda, Kosuke, Nagadomi, Yasushi
• Granted Patent: US 8,484,432 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A memory system includes a non-volatile memory constituted by blocks each of which is an erase unit constituted by pages each of which is a write/read unit constituted by memory cells; a random access memory temporarily storing data which is written in or read from the non-volatile memory; and a controller controlling the non-volatile memory and the random access memory, wherein the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and the controller changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.

Claims

1. A memory system comprising:

a non-volatile memory constituted by a plurality of blocks each of which is an erase unit constituted by a plurality of pages each of which is a write/read unit constituted by a plurality of memory cells each of which has a floating gate and can erase, write, and read data electrically;

a random access memory temporarily storing data which is written in or read from the non-volatile memory; and

a controller controlling the non-volatile memory and the random access memory, wherein

the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and

the controller dynamically changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.

2. The memory system according to claim 1, wherein the controller reduces the number of the blocks in the cache area and increases number of blocks to be erased in the main memory area when an amount of data stored in the main memory area is larger than a predetermined value.

3. The memory system according to claim 1, wherein the controller determines whether data to be written that is received from outside of the non-volatile memory is stored in the main memory area or the cache area on the basis of the capacity of the data to be written.

4. The memory system according to claim 2, wherein the controller determines whether data to be written that is received from outside of the non-volatile memory is stored in the main memory area or the cache area on the basis of the capacity of the data to be written.

5. The memory system according to claim 1, wherein the cache area stores data that has with higher access probability as compared to data stored in the main memory area.

6. The memory system according to claim 2, wherein the cache area stores data that has with higher access probability as compared to data stored in the main memory area.

7. The memory system according to claim 3, wherein the cache area stores data that has with higher access probability as compared to data stored in the main memory area.

8. The memory system according to claim 2, wherein

the controller searches for a first logical address assigned to one of the second management units to store the data to be written received from outside of the non-volatile memory in the cache area, and

when the amount of data stored in the main memory area is larger than a predetermined value, the controller reduces number of the first logical addresses to be searched so as to reduce the number of the blocks in the cache area and increase the number of the blocks in the main memory area.

9. The memory system according to claim 1, wherein

in the main memory area, data is written in an empty memory area using a write-once method, and

the data is written in a part of the cache area serving as a write-once area in the main memory area.

10. A memory system comprising:

a flash EEPROM memory that its read/write unit is different from its erase unit and a RAM; and

a controller controlling the flash EEPROM memory and the RAM, wherein

the flash EEPROM memory has at least a first storage area and a second storage area which have different applications for data to be stored from each other,

the controller has a function of managing a first list storing data which indicates block areas being used among erase units of the flash EEPROM memory, a second list storing data which indicates unused or used block areas, and a third list and a fourth list which are provided for ensuring an erase interval for the flash EEPROM memory,

the third list and the fourth list store data indicating the used block areas for the first storage area and the second storage area, respectively, and

the third list and the fourth list store data have different numbers of data entries from each other.

11. The memory system according to claim 10, wherein the first storage area is a main storage area, the second storage area is a cache area, and

number of data entries in the third list is smaller than number of data entries in the fourth list for the cache area.

12. The memory system according to claim 10, wherein, when the data stored in the third or the fourth list is full, the controller preferentially registers data of the block area, which serves as the erase unit and is assigned earliest in the third or the fourth list, in the second list.

13. The memory system according to claim 10, wherein the controller preferentially registers data in the second list,

the data is continuously stored in the third or the fourth list for a certain period of time.

14. The memory system according to claim 11, wherein if there is not any data to be preferentially registered in the first list among the data in the second list, the controller selects data from the third list when the data to be registered in the first list is used in the main storage area or selects data from the fourth list when the data to be registered in the first list is used in the cache area, and the controller registers the selected data in the first list.

15. The memory system according to claim 14, wherein, when data is selected from the third or the fourth list, the controller successively selects the data of the block area, which serves as the erase unit and is assigned earliest, according to the order of storing in the third or the fourth list.